An Open Image Denoise 2.2 release candidate was released earlier today—as discovered by Phoronix's founder and principal writer; Michael Larabel. Intel's dedicated website has not been updated with any new documentation or changelogs (at the time of writing), but a GitHub release page shows all of the crucial information. Team Blue's open-source oneAPI has been kept up-to-date with the latest technologies—not only limited to Intel's stable of Xe-LP, Xe-HPG and Xe-HPC components—the Phonorix article highlights updated support on competing platforms. The v2.2 preview adds support for Meteor Lake's integrated Arc graphics solution, and additional "denoising quality enhancements and other improvements."

Non-Intel platform improvements include updates for Apple's M-series chipsets, AArch64 processors, and NVIDIA CUDA. OIDn 2.2-rc: "adds Metal device support for Apple Silicon GPUs on recent versions of macOS. OIDn has already been supporting ARM64/AArch64 for Apple Silicon CPUs while now Open Image Denoise has extended that AArch64 support to work on Windows and Linux too. There is better performance in general for Open Image Denoise on CPUs with this forthcoming release." The changelog also highlights a general improvement performance across processors, and a fix that resolves a crash incident: "when releasing a buffer after releasing the device."

Supermicro, Inc. (NASDAQ: SMCI), a Total IT Solution Provider for Cloud, AI/ML, Storage, and 5G/Edge, will be showcasing its latest generation of systems that accelerate workloads for the entire Telco industry, specifically at the edge of the network. These systems are part of the newly introduced Supermicro Intel-based product line; the better, faster, and greener systems based on the brand new 4th Gen Intel Xeon Scalable processors (formerly codenamed Sapphire Rapids) that deliver up to 60% better workload-optimized performance. From a performance standpoint these new systems that demonstrate up to 30X faster AI inference speedups on large models for AI and edge workloads with the NVIDIA H100 GPUs. In addition, Supermicro systems support the new Intel Data Center GPU Max Series (formerly codenamed Ponte Vecchio) across a wide range of servers. The Intel Data Center GPU Max Series contains up to 128 Xe-HPC cores and will accelerate a range of AI, HPC, and visualization workloads. Supermicro X13 AI systems will support next-generation built-in accelerators and GPUs up to 700 W from Intel, NVIDIA, and others.

Supermicro's wide range of product families is deployed in a broad range of industries to speed up workloads and allow faster and more accurate decisions. With the addition of purpose-built servers tuned for networking workloads, such as Open RAN deployments and private 5G, the 4th Gen Intel Xeon Scalable processor vRAN Boost technology reduces power consumption while improving performance. Supermicro continues to offer a wide range of environmentally friendly servers for workloads from the edge to the data center.

Intel in an interview with Hardwareluxx shed more light on its second generation Xe graphics architecture, codenamed "Battlemage." There will be two key variants of "Battlemage,"—Xe2-LPG and Xe2-HPG. The Xe2-LPG (low-power graphics) architecture is a slimmed-down derivative of "Battlemage" that's optimized for low-power. It is meant for iGPUs (integrated graphics), particularly upcoming "disaggregated" Intel Core processors in which the iGPU exists on Graphics Tiles (chiplets). The iGPU powering the upcoming Core "Meteor Lake" processor is rumored to meet the full DirectX 12 Ultimate feature-set (something Xe-LP doesn't), and so it's likely that Xe2-LPG is getting its first outing with that processor. The Xe2-HPG (high performance graphics) architecture is designed squarely for discrete GPUs—either desktop graphics cards, or mobile discrete GPUs hardwired into laptops.

In the interview, Intel talked about how its first-generation Xe graphics IP had at least four separate product verticals based on the scalability of the product, and the specific application (Xe-LP for iGPUs and tiny dGPUs, Xe-HPG for client- and pro-vis discrete GPUs, Xe-HPC for scalar compute processors, and Xe-HP for data-center graphics). The company eventually axed Xe-HP as it felt the Xe-HPG and Xe-HPC architectures adequately addressed this segment. With AXG (accelerated compute group) being split up between the CCG (client computing group) and DCG (data-center group); Xe2-LPG and Xe2-HPG will be developed primarily under CCG, with a client and pro-visualization focus; while Xe-HPC will be developed as a scalar-compute architecture by DCG, which effectively leaves the Intel Arc Graphics team with just two verticals—to deliver a feature-rich iGPU for its next-generation Core processors, and a performance discrete GPU lineup so it can eat away market-share from NVIDIA and AMD—hopefully with better time-to-market.

In advance of Supercomputing '22 in Dallas, Intel Corporation has introduced the Intel Max Series product family with two leading-edge products for high performance computing (HPC) and artificial intelligence (AI): Intel Xeon CPU Max Series (code-named Sapphire Rapids HBM) and Intel Data Center GPU Max Series (code-named Ponte Vecchio). The new products will power the upcoming Aurora supercomputer at Argonne National Laboratory, with updates on its deployment shared today.

The Xeon Max CPU is the first and only x86-based processor with high bandwidth memory, accelerating many HPC workloads without the need for code changes. The Max Series GPU is Intel's highest density processor, packing over 100 billion transistors into a 47-tile package with up to 128 gigabytes (GB) of high bandwidth memory. The oneAPI open software ecosystem provides a single programming environment for both new processors. Intel's 2023 oneAPI and AI tools will deliver capabilities to enable the Intel Max Series products' advanced features.

During the International Supercomputing Conference on May 31, 2022, in Hamburg, Germany, Jeff McVeigh, vice president and general manager of the Super Compute Group at Intel Corporation, announced Rialto Bridge, Intel's data center graphics processing unit (GPU). Using the same architecture as the Intel data center GPU Ponte Vecchio and combining enhanced tiles with Intel's next process node, Rialto Bridge will offer up to 160 Xe cores, more FLOPs, more I/O bandwidth and higher TDP limits for significantly increased density, performance and efficiency.

"As we embark on the exascale era and sprint towards zettascale, the technology industry's contribution to global carbon emissions is also growing. It has been estimated that by 2030, between 3% and 7% of global energy production will be consumed by data centers, with computing infrastructure being a top driver of new electricity use," said Jeff McVeigh, vice president and general manager of the Super Compute Group at Intel Corporation.

Intel is reportedly looking to disrupt the cryptocurrency mining hardware business with fixed-function ASICs that either outperform GPUs, or end up with lower enough performance/Watt or performance/Dollar to take make GPUs unviable as a mining hardware option. The company is planning to unveil its first such product, codenamed "Bonanza Mine," an ASIC purpose-built for Bitcoin mining.

Since it's an ASIC, "Bonanza Mine" doesn't appear to be a re-purposed Xe-HPC processor, or even an FPGA that's been programmed to mine Bitcoin. It's a purpose-built piece of silicon. Intel will unveil "Bonanza Mine" at the 2022 ISSCC Conference. It describes the chip as being an "ultra low-voltage energy-efficient Bitcoin mining ASIC," putting power-guzzling GPUs on notice. If Intel can clinch Bitcoin with "Bonanza Lake," designing ASICs for other cryptocurrencies is straightforward. With demand from crypto-miners slashed, graphics cards will see a tremendous fall in value, forcing scalpers to cut prices.

Intel has dropped plans to build Xe-HP server GPUs commercially. This line of products would have powered cloud-based graphics rendering instances, for cloud-gaming or cloud-rendering applications. An announcement to this effect came from Raja Koduri, overseeing the development and monetization of Xe. Koduri stated that Xe-HP based instances were originally set up to power Intel's oneAPI devcloud as a software development vehicle for oneAPI and the upcoming Aurora supercomputer of the Argonne National Laboratory.

The company will now focus on Xe as a compute accelerator in the form of Xe-HPC "Ponte Vecchio," and discrete graphics in the client segment, leveraging the Xe-HPG graphics architecture. The smallest derivatives, the Xe-LP, powers integrated graphics solutions found in the company's Core processors (11th Gen and later). Back in the August 2021 Architecture Day presentation, Intel's technical brief for Xe HPC revealed that the silicon itself features certain on-die hardware relevant to graphics rendering (more here). This would have gone on to power the Xe-HP server GPU solutions.

AMD is preparing an update to its compute accelerator lineup with the new MI250X. Based on the CDNA2 architecture, and built on existing 7 nm node, the MI250X will be accompanied by a more affordable variant, the MI250. According to leaks put out by ExecutableFix, the MI250X packs a whopping 110 compute units (7,040 stream processors), running at 1.70 GHz. The package features 128 GB of HBM2E memory, and a package TDP of 500 W. As for speculative performance numbers, it is expected to offer double-precision (FP64) throughput of 47.9 TFLOP/s, ditto full-precision (FP32), and 383 TFLOP/s half-precision (FP16 and BFLOAT16). AMD's MI200 "Aldebaran" family of compute accelerators are expected to square off against Intel's "Ponte Vecchio" Xe-HPC, and NVIDIA Hopper H100 accelerators in 2022.

Intel has begun sampling its Xe-HPG (High performance Gaming) products to ecosystem partners, which will allow them to verify performance, power, stability and board characteristics that are necessary variables in product development and launch. The information comes courtesy of Intel, who has updated its graphics product roadmap regarding DG2 sampling and for its Xe-HPC (High Performance Computing) products as well. Xe HPC products (codenamed Ponte Vecchio after a beautiful Florentine bridge) have now achieved power-on capabilities and are undergoing validation before subsequent steps in the hardware development workflow.