Glossary of Terms

Below is a list of technical terms relevant to overclocking the memory of a Ryzen-powered machine. Ryzen uses the industry-standard DDR4 memory architecture, so you may be familiar with some of these terms. Some other terms are new and specific to the "Zen" architecture.

• SOC voltage - system on a chip voltage; responsible for the voltage related to the memory controller.
  Limit: up to 1.2 V.
• DRAM boot voltage - voltage at which memory training takes place at system start-up.
  Limit: up to 1.45–1.50 V.
• VDDP voltage - voltage for the transistor that sets memory contents.
  Limit: up to 1.1 V.
• CLDO VDDP voltage - voltage for the DDR4 PHY on the SoC. The DDR4 PHY or physical-layer interface converts information from the memory controllers to a format the DDR4 memory modules can understand.
  Somewhat counterintuitively, lowering VDDP can often be more beneficial for stability than raising CLDO_VDDP. Advanced overclockers should also know that altering CLDO VDDP can move or resolve memory holes. Small changes to VDDP can have a big effect, and VDDP cannot not be set to a value greater than VDIMM - 0.1 V (not to exceed 1.05 V). A cold reboot is required if you alter this voltage.
  Limit: up to 1.0 V.
• VPP (VPPM) voltage - voltage that determines how reliably a DRAM row gets accessed.
  Limit: up to 2.7 V.
• Vref voltage - memory reference voltage; "Configures" both the CPU and the memory module with the voltage level that separates what is to be considered a "0" or a "1"; i.e., voltages found on the memory bus below MEMVREF are to be considered a "0," and voltages above this level are to be considered a "1." By default, this voltage level is half of VDDIO (a.k.a. 0.500x). Some motherboards allow the user to change this ratio, usually through two options: (1) "DRAM Ctrl Ref Voltage" (for the control lines from the memory bus; JEDEC's official name for this voltage is VREFCA), and (2) "DRAM Ctrl Data Ref Voltage" (for the data lines from the memory bus; JEDEC's official name is "VREFDQ"). These options are configured as a multiplier.
• VTT DDR voltage - voltage used to control the impedance of the bus in order to achieve the high speed and maintain signal integrity. This is done by resistor parallel termination.
• PLL (1P8) voltage - This option can be used to stabilize the CPU at high BCLKs.
  Limit: up to 1.9 V.
• CAD_BUS - Command & Address bus; for those who are able to train the memory at high speeds (>=3466MHz), but are unable to stabilize it due to signaling issues. I suggest you try decreasing "Command & Address" related drive currents (increasing the resistance).
  Limit: None.
• CAD_BUS timings - transceiver delay. Values set a bit mask.
  Limit: None.
• procODT - resistance value, in ohms, that determines how a completed memory signal is terminated. Higher values can help stabilize higher data rates.
  Limit: None.
• RTT (Signal Integrity Optimizations) - the use of multiple ranks of DRAM on the DDR4 interface requires additional options for selecting the on-die terminating resistance for individual ranks.
  DDR4 DRAM offers a range of terminating resistance values. The specific DQ pin receiver resistance presented to the interface is selected by a combination of the initial chip configuration and the DRAM operating command if dynamic on-die termination is enabled.
  Limit: None.
• Geardown Mode - allows the DRAM device to run off its internally-generated ½ rate clock for latching on the command or address buses.
  ON is the default for speeds greater than DDR4-2667. However, the benefit of ON vs. OFF will vary from memory kit to memory kit. Enabling Geardown Mode will override your current command rate.
• Power Down Mode - can modestly save system power at the expense of higher DRAM latency by putting DRAM into a quiescent state after a period of inactivity.