Memory Controller Architecture

AMD's Zen 5 architecture is built around a multi-die design, where the I/O die (IOD) is separate from the compute dies, commonly known as Core Complex Dies (CCDs). This separation is a defining feature of AMD's modern Ryzen platforms, allowing the I/O Die to handle all data traffic between the CPU cores, memory, and other system components. By isolating the memory controller and other I/O functions in a dedicated die, AMD can optimize the design and thermal characteristics of the CCDs, focusing them solely on compute tasks. This not only improves efficiency but also helps scale performance across different configurations of core counts and memory speeds, especially as DDR5 introduces higher bandwidth demands.

Having a distinct I/O die allows AMD to manufacture the CCDs and IOD on different process nodes, which provides flexibility in optimizing each component for its specific function. For example, while the CCDs may be produced on a leading-edge process for better performance, the IOD can be manufactured on a more mature node that balances performance with power efficiency, and it helps reduce cost, too.

FCLK vs UCLK vs MCLK

In AMD's DDR5 memory architecture, the clocking system is divided into three key components: FCLK, UCLK, and MCLK, each playing a crucial role in memory performance.

• FCLK (Infinity Fabric Clock) governs the frequency of the Infinity Fabric, which links the compute dies, I/O die, and other components.
• UCLK (Unified Memory Controller Clock) controls the speed of the memory controller within the I/O die, how fast it can forward the data flowing between Infinity Fabric and the chips on the memory module.
• MCLK (Memory Clock) directly corresponds to the speed of the DDR5 memory, this is the "DDR5-6000" that memory vendors list in their spec sheets. Please note that due to the double-data-rate (DDR) nature of DDR5, the actual clock frequency is half that, i.e. 3000 MHz for DDR5-6000.

In an ideal configuration, these three clocks operate in a synchronized manner—the 1:1:1 ratio (FCLK:UCLK:MCLK), that you might have seen before. In this configuration latency between the processor and memory is at a minimum, because data can flow right through. However, as DDR5 speeds increase, maintaining this ratio becomes more challenging, which is why AMD enabled a decoupled mode, which lets each component operate at or near its own maximum frequency.

Decoupling the clocks will introduce additional latency because the memory controller and memory are no longer perfectly synchronized, leading to small delays in transfers while data is buffered for a short moment. However, this trade-off is often necessary to stabilize the system at higher DDR5 speeds, as maintaining a 1:1:1 ratio becomes increasingly difficult due to the limits of the Infinity Fabric and memory controller at extreme frequencies.

In the past, AMD has recommended running at a 1:1:1 mode, but this has changed with Zen 5. Now the recommendation is Auto:1:1. This means that you should keep FCLK at around 2000 MHz, which is set automatically by the BIOS. Actually, on my board it gets set to 2100 MHz, which is what I used for all testing.

1:1 vs 1:2

By default, AMD's Zen 5 processors switch from the 1:1 mode to a 1:2 mode for all memory speeds higher than 6000 MT/s. DDR5-6000 runs at 1:1, which is part of the reason why AMD selected it as the sweet spot. Due to the way AMD designed their memory controller, it's unable to run at the high speeds required by modern DDR5.


The table above shows the relationship between MCLK and UCLK at various DDR speeds. As you can see, once you go above DDR5-6000, the memory controller has to run at MCLK of over 3000 MHz, which is getting close to its maximum frequency limits.

When the 1:2 mode is active, the memory runs at twice the frequency of the memory controller, which means the memory controller can run at lower speeds, which it can handle better. This lets you achieve higher memory speeds without compromising the stability of the memory controller. While memory bandwidth is increased, additional latency is introduced, because the memory controller has to manage the data flow without being able to synchronize perfectly with the memory clock.

Test System

• The DDR5 testing scores are with the power limit disabled using PBO. With the default power limit, the additional power consumption in the memory controller due to the higher DRAM speed will take away some power headroom from the CPU cores. This is explained on the next page.