Architecture

The Ada graphics architecture heralds the third generation of the NVIDIA RTX technology, an effort toward increasing the realism of game visuals by leveraging real-time ray tracing, without the enormous amount of compute power required to draw purely ray-traced 3D graphics. This is done by blending conventional raster graphics with ray traced elements such as reflections, lighting, and global illumination, to name a few. The 3rd generation of RTX introduces the new higher IPC "Ada" CUDA core, 3rd generation RT core, 4th generation Tensor core, and the new Optical Flow Processor, a component that plays a key role in generating new frames without involving the GPU's main graphics rendering pipeline. The GeForce Ada graphics architecture driving the RTX 4080 Super leverages the TSMC 5 nm EUV foundry process to increase transistor counts.



The GeForce RTX 4080 Super is based on the same 5 nm AD103 silicon as the original RTX 4080. As a SKU, it has a lot in common with the RTX 2080 Super, which had maxed out the TU104 silicon, while the original RTX 2080 wasn't too far behind. The AD103 is NVIDIA's second largest silicon, powering not just the RTX 4080 and the RTX 4080 Super, but also the mobile RTX 4090. This 379 mm² beast packs nearly 46 billion transistors—more than that of the previous generation flagship GA102. It has 80 streaming multiprocessors, and since the RTX 4080 Super maxes the chip out, all 80 are enabled. This gives the RTX 4080 Super a phenomenal CUDA core count of 10,240, with 320 Tensor cores, 80 RT cores, 320 TMUs, and all of the chip's 112 ROPs. The AD103 features a 256-bit wide memory interface, and the RTX 4080 Super continues to get 16 GB of memory, running at 23 Gbps—higher than the 22.4 Gbps of the RTX 4080.

The AD103 features a PCI-Express 4.0 x16 host interface along with support for PCI resizable BAR; and its 256-bit wide GDDR6X memory interface. The GigaThread Engine serves as the main workflow controller for the GPU, dispatching work among the GPU's 7 graphics processing clusters (GPCs). Each GPC shares a Raster Engine and render backends among six texture processing clusters (TPCs), the indivisible subunit of the GPU; one of the GPCs has just four TPCs. Each TPC has two Streaming Multiprocessors (SM), and a Polymorph unit. Each SM contains 128 CUDA cores across four partitions. Half of these CUDA cores are pure-FP32; while the other half is capable of FP32 or INT32. The SM retains concurrent FP32+INT32 math processing capability. The SM also contains a 3rd generation RT core, four 4th generation Tensor cores, some cache memory, and four TMUs. One of the seven GPCs on the AD103 physically only has four TPCs.

With 80 SM that have 128 CUDA cores, each; we arrive at 10,240 CUDA cores. NVIDIA says that the RTX 4080 Super maxes out the AD103 silicon; and this statement is 99.999% true. The AD103 has four NVDEC and two NVENC units on the silicon; but for the RTX 4080 Super, just like the RTX 4080, three of these NVDEC units are disabled. This is irrelevant for a GeForce RTX product, and NVIDIA only put those large numbers of NVDEC units for pro-visualization graphics cards, such as the RTX 5000 Ada.

3rd Gen RT Core and Ray Tracing

The 3rd generation RT core accelerates the most math-intensive aspects of real-time ray tracing, including BVH traversal. Displaced micro-mesh engine is a revolutionary feature introduced with the new 3rd generation RT core. Just as mesh shaders and tessellation have had a profound impact on improving performance with complex raster geometry, allowing game developers to significantly increase geometric complexity; DMMs is a method to reduce the complexity of the bounding-volume hierarchy (BVH) data-structure, which is used to determine where a ray hits geometry. Previously, the BVH had to capture even the smallest details to properly determine the intersection point. Ada's ray tracing architecture also receives a major performance uplift from Shader Execution Reordering (SER), a software-defined feature that requires awareness from game-engines, to help the GPU reorganize and optimize worker threads associated with ray tracing.


The BVH now needn't have data for every single triangle on an object, but can represent objects with complex geometry as a coarse mesh of base triangles, which greatly simplifies the BVH data structure. A simpler BVH means less memory consumed and helps to greatly reduce ray tracing CPU load, because the CPU only has to generate a smaller structure. With older "Ampere" and "Turing" RT cores, each triangle on an object had to be sampled at high overhead, so the RT core could precisely calculate ray intersection for each triangle. With Ada, the simpler BVH, plus the displacement maps can be sent to the RT core, which is now able to figure out the exact hit point on its own. NVIDIA has seen 11:1 to 28:1 compression in total triangle counts. This reduces BVH compile times by 7.6x to over 15x, in comparison to the older RT core; and reducing its storage footprint by anywhere between 6.5 to 20 times. DMMs could reduce disk- and memory bandwidth utilization, utilization of the PCIe bus, as well as reduce CPU utilization. NVIDIA worked with Simplygon and Adobe to add DMM support for their tool chains.

Opacity Micro Meshes

Opacity Micro Meshes (OMM) is a new feature introduced with Ada to improve rasterization performance, particularly with objects that have alpha (transparency data). Most low-priority objects in a 3D scene, such as leaves on a tree, are essentially rectangles with textures on the leaves where the transparency (alpha) creates the shape of the leaf. RT cores have a hard time intersecting rays with such objects, because they're not really in the shape that they appear (they're really just rectangles with textures that give you the illusion of shape). Previous-generation RT cores had to have multiple interactions with the rendering stage to figure out the shape of a transparent object, because they couldn't test for alpha by themselves.


This has been solved by using OMMs. Just as DMMs simplify geometry by creating meshes of micro-triangles; OMMs create meshes of rectangular textures that align with parts of the texture that aren't alpha, so the RT core has a better understanding of the geometry of the object, and can correctly calculate ray intersections. This has a significant performance impact on shading performance in non-RT applications, too. Practical applications of OMMs aren't just low-priority objects such as vegetation, but also smoke-sprites and localized fog. Traditionally there was a lot of overdraw for such effects, because they layered multiple textures on top of each other, that all had to be fully processed by the shaders. Now only the non-opaque pixels get executed—OMMs provide a 30 percent speedup with graphics buffer fill-rates, and a 10 percent impact on frame-rates.

DLSS 3 Frame Generation

DLSS 3 introduces a revolutionary new feature that promises a doubling in frame-rate at comparable quality, it's called AI frame-generation. Building on DLSS 2 and its AI super-resolution (scaling up a lower-resolution frame to native resolution with minimal quality loss); DLSS 3 can generate entire frames simply using AI, without involving the graphics rendering pipeline, it's also possible to enable frame generation at native resolution without upscaling. Later in the article, we will show you DLSS 3 in action.


Every alternating frame with DLSS 3 is hence AI-generated, without being a replica of the previous rendered frame. This is possible only on the Ada graphics architecture, because of a hardware component called the optical flow accelerator (OFA), which assists in predicting what the next frame could look like, by creating what NVIDIA calls an optical flow-field. OFA ensures that the DLSS 3 algorithm isn't confused by static objects in a rapidly-changing 3D scene (such as a race sim). The process heavily relies on the performance uplift introduced by the FP8 math format of the 4th generation Tensor core. A third key ingredient of DLSS 3 is Reflex. By reducing the rendering queue to zero, Reflex plays a vital role in ensuring that latency with DLSS 3 enabled is at an acceptable level. A combination of OFA and the 4th Gen Tensor core is why the Ada architecture is required to use DLSS 3, and why it won't work on older architectures.