The Alder Lake-S Silicon

As we mentioned earlier, Intel still does not subscribe to the modular CPU core chiplet approach to build high core-count processors used by AMD. Its hybrid architecture approach, though, could be described as being just as innovative. The "Alder Lake-S" silicon is a monolithic die fabricated on the Intel 7 process, known earlier as 10 nm Enhanced SuperFin. The silicon has essentially the same layout as Intel client processor dies from the past, with a centralized last-level cache (LLC, or L3 cache) and a bi-directional ringbus connecting the various blocks (parts of the processor).

The most important blocks are the CPU cores, and there are 16 of them on Alder Lake-S. Eight of these are the larger Golden Cove P-cores, and eight of these are Gracemont E cores. Each of the eight P-cores has its dedicated ring-stop. Groups of four E cores make up an E-core cluster. There are two such E-core clusters on Alder Lake-S, each with a ring-stop. From what we can tell, while you can disable individual P-cores available on your SKU, you can only disable E cores on a per-cluster basis. You also must have at least one P-core active—so you can't run the CPU with only E cores. You can disable all E cores for a pure P-core processor, though.

The Alder Lake-S silicon features 30 MB of shared L3 cache that's accessible by all components on the silicon, including the P-cores, E-core clusters, iGPU, memory controllers, PCIe root-complex, and other uncore components. Each of the eight P-cores has a dedicated 1.25 MB of L2 cache. Each E-core Cluster has a 2 MB L2 cache that's shared among the four E cores. We'll describe the L1 caches that deals with each of the two CPU core types on the next page.

Intel UHD 770 Graphics (Xe LP)

The Alder Lake-S die features an iGPU based on the same Xe LP graphics architecture as the one found in previous-gen "Rocket Lake-S." For the six SKUs being launched today, the iGPU model is the "Intel UHD 770." This SKU features all 32 Xe execution units available on the silicon. We've extensively tested the Xe LP-based iGPU on the Core i9-11900K and found that while it's good enough for the modern PC with high-resolution displays, high-framerate video playback, etc., it's not a suitable gaming solution for all titles even when running at the lowest-possible settings. You still get hardware-accelerated decoding of AV1, HEVC, and other modern video formats, along with most modern HDR standards. The iGPU's display engine appears to be unchanged from the previous generation, with support for HDMI 2.1 and DisplayPort 1.4.

Memory and PCIe

The 12th Gen Core Alder Lake architecture heralds the biggest update of platform I/O in several generations, letting Intel get ahead of AMD in this space. It will also drive the mainstreaming of new memory and PCIe standards. The star attraction with Alder Lake is support for DDR5 memory without losing support for current-gen DDR4. The processor supports up to 128 GB of DDR5-4800 memory, with a total of four 40-bit wide channels (two per DIMM). Of course, you can go higher in memory speeds, but that's considered overclocking. Unlike DDR4, which uses a single 64-bit wide channel per DIMM, DDR5 features two 40-bit channels. In that sense, the DDR5 interface on Alder Lake can be called "quad-channel," although each of these channels has a lower bus-width. The processor retains support for dual-channel DDR4-3200 (64-bit per DIMM).

To ease the transition between DDR4 and DDR5, especially given the current environment of steep hardware prices, Intel decided to get its motherboard partners to release a substantial lineup of motherboards with DDR4 memory slots, besides those with DDR5. We are yet to come across boards that have both DDR4 and DDR5 slots, although we can't see why such contraptions aren't possible as long as you choose to run the same type of memory and don't expect to run DDR4 and DDR5 at the same time.

The other major I/O update is with PCI-Express. Alder Lake-S debuts PCI-Express Gen 5 to the client segment. The processor puts out 16 PCI-Express Gen 5 lanes, which are typically dedicated to the motherboard's PCI-Express Graphics (PEG) slot. Some motherboards could use PCIe Gen 5-compliant lane switches or splitters to put out up to two x16 slots (x8/x8 with both populated) or even pull out some lanes toward M.2 NVMe slots with PCIe Gen 5 wiring. Speaking of which, besides the sixteen Gen 5 lanes, the processor also puts out four Gen 4 lanes toward a CPU-attached M.2 NVMe slot.

The chipset bus also gets a massive upgrade, with Intel introducing the new Direct Media Interface (DMI) Gen 4. Alder Lake-S supports up to eight DMI Gen 4 lanes, effectively doubling the bandwidth between processor and chipset. The Z690 chipset being launched today utilizes all eight DMI lanes. We don't know whether other upcoming chipsets have narrower interfaces, but Intel has used DMI bus-width as a point for segmenting the top-tier chipset from mid-tier ones. B560, for example, only supports four-lane DMI Gen 3 on even Rocket Lake-S processors that are capable of eight lanes. DMI Gen 4 x8 is an enormous chipset bus bandwidth uplift—128 Gbps per direction. Compare this to the 32 Gbps per direction of 10th Gen Core processors with their companion 400-series chipsets. Such an uplift in chipset bus bandwidth was necessitated by modern downstream connectivity standards, such as Thunderbolt 4, USB 3.2x2, 10 GbE Ethernet, Wi-Fi 6E, or the growing popularity of NVMe RAID among video editing professionals. We'll talk about chipset-attached connectivity on the following pages.