Multiple hardware versions found.
Performance could vary due to unannounced flash/controller changes.
Capacity: | 1 TB (1024 GB) |
---|---|
Variants: | 256 GB 512 GB 1 TB 2 TB |
Hardware Versions: | |
Overprovisioning: | 70.3 GB / 7.4 % |
Production: | Active |
Released: | 2021 |
Part Number: | IR-SSDPR-P34B-01T-80 |
Market: | Consumer |
Form Factor: | M.2 2280 (Double-Sided) |
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Interface: | PCIe 3.0 x4 |
Protocol: | NVMe 1.3 |
Power Draw: | Unknown |
Manufacturer: | Phison |
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Name: | PS5012-E12S-32 |
Architecture: | ARM 32-bit Cortex-R5 |
Core Count: | Quad-Core |
Frequency: | 667 MHz |
Foundry: | TSMC |
Process: | 12 nm |
Flash Channels: | 8 @ 667 MT/s |
Chip Enables: | 4 |
Controller Features: | DRAM (enabled) |
Manufacturer: | Toshiba |
---|---|
Name: | BiCS3 |
Type: | TLC |
Technology: | 64-layer |
Speed: | 533 MT/s |
Capacity: | 4 chips @ 2 Tbit |
ONFI: | 3.2 |
Toggle: | 2.0 |
Topology: | Charge Trap |
Process: | 19 nm |
Dies per Chip: | 8 dies @ 256 Gbit |
Planes per Die: | 2 |
Decks per Die: | 2 |
Read Time (tR): | 80 µs |
Program Time (tProg): | 695 µs |
Die Read Speed: | 400 MB/s |
Die Write Speed: | 46 MB/s |
Endurance: (up to) |
3000 P/E Cycles
(30000 in SLC Mode) |
Page Size: | 16 KB |
Block Size: | 768 Pages |
Plane Size: | 1478 Blocks |
Type: | DDR4-2400 CL17 |
---|---|
Name: | SK Hynix H5AN4G8NBJR-UHC |
Capacity: |
1024 MB
(2x 512 MB) |
Organization: | 4Gx8 |
Sequential Read: | 3,200 MB/s |
---|---|
Sequential Write: | 3,000 MB/s |
Random Read: | 250,000 IOPS |
Random Write: | 500,000 IOPS |
Endurance: | 600 TBW |
Warranty: | 5 Years |
MTBF: | 1.8 Million Hours |
Drive Writes Per Day (DWPD): | 0.3 |
SLC Write Cache: | Yes |
TRIM: | Yes |
---|---|
SMART: | Yes |
Power Loss Protection: | No |
Encryption: |
|
RGB Lighting: | No |
PS5 Compatible: | No |
Controller:2 main cores using Cortex-R5 clocked at 667 MHz with CoXProcessor technology (one additional dual-core) Cortex-R5 clocked at a lower clock for better efficience. The difference between this revision and the E12 revision is that this has a nichel IHS to improve the temperature, a smaller size, smaller node (12nm TSMC FinFET) and this works with less DRAM capacity. NAND Die:Read latency: |