Tuesday, April 17th 2018
AMD Readies Z490 Chipset with More (and Faster) PCIe Lanes
AMD is reportedly readying a new high-end motherboard chipset positioned higher than even its upcoming X470 chipset, which makes its market debut on April 19. The new Z490 chipset, as it's called, is emerging to be significantly different from X470, and could finally overcome its biggest limitation - downstream PCIe connectivity. While the X470, like its predecessor, puts out just 8 downstream PCIe lanes, which are PCI-Express gen 2.0 at that, the new Z490 will put out a total of 12 PCI-Express gen 3.0 downstream lanes, which will power additional bandwidth-hungry devices, such as additional M.2 slots, external USB 3.1 controllers, 10 GbE controllers, etc. The Z490 was first leaked through a GIGABYTE Aorus internal presentation.
In its current implementation, socket AM4 motherboards have a total of 24 PCI-Express gen 3.0 lanes from the AM4 SoC, besides 6-8 gen 2.0 lanes from the chipset. From this SoC budget, 16 lanes are allocated for PEG (PCI-Express Graphics), 4 lanes as chipset-bus (connecting the SoC with the chipset), and the remaining 4 lanes powering one 32 Gbps M.2 slot. Additional M.2 slots are either gen 2.0, from the chipset's downstream lane budget, or split from the PEG budget. The Z490 overcomes this with a downstream PCIe root complex that's not just 50% broader, but also twice as fast, with PCI-Express gen 3.0. The rest of its feature-set appears to be identical to the X470. There's no timeline on when we can expect Z490 to launch.
Source:
VideoCardz
In its current implementation, socket AM4 motherboards have a total of 24 PCI-Express gen 3.0 lanes from the AM4 SoC, besides 6-8 gen 2.0 lanes from the chipset. From this SoC budget, 16 lanes are allocated for PEG (PCI-Express Graphics), 4 lanes as chipset-bus (connecting the SoC with the chipset), and the remaining 4 lanes powering one 32 Gbps M.2 slot. Additional M.2 slots are either gen 2.0, from the chipset's downstream lane budget, or split from the PEG budget. The Z490 overcomes this with a downstream PCIe root complex that's not just 50% broader, but also twice as fast, with PCI-Express gen 3.0. The rest of its feature-set appears to be identical to the X470. There's no timeline on when we can expect Z490 to launch.
27 Comments on AMD Readies Z490 Chipset with More (and Faster) PCIe Lanes
They'll probably time this with Intel Z390 launch. "We too have a new chipset, and it's 100 numbers more advanced."
This also explains why there's no Crosshair VII Extreme yet.
why not X490??? man....
cant they create their own names than copying...this is getting ridiculous...making it more confusing for the consumer.
i guess thats what u expect from a low-tier company like (AMD) $10 Billion vs the tech giants & market leader Intel($240 Billion) or Nvidia ($130 Billion)....
or maybe AMD should have named it X470X Series...that sounds familiar.. ( ͡° ͜ʖ ͡°)
Z490 naming is obviously to one-up Intel's Z390. Not all Intel does is worth copying tho. This is the prime example.
I also partially blame ASMedia for this a they are the one making these chipsets.
Intel said in an interview...they dont mind taking risks..like now they are investing billions in Driver-less AI solutions..
on the other hand Nvidia..they are profitable in server business & AI & other data center -technologies..
well isnt it enough to be making billions in just sellin GPU??? well they are a GPU tech company afterall controlling 85% of the entire market in the entire world.
Your source? AFAIK Intel have them beat in PC while QC/Apple/PowerVR/ARM beat them in the mobile space, AMD has a big lead in consoles.
They'd have to unlock more lanes on the CPU itself which I think they won't do for compatibility and validation reasons.
I won't put too much stock into what's probably a fake leaked slide but if so there's probably quite a few limitations that causes them to launch a new chipset.
AMD doesnt even have a mobile space..All that can save them are a CryptoMiners & that homerun is going to end soon..
"AMD has a big lead in consoles.."
Then why were they having 5+years of consective loss in thier balance sheet
Nvidia didnt want to make for PS4 or Xbox because it was not too profitable..& was not worth it & they got hardware 2X times powerful selling like hotcakes..
"i dont want to go offtopic anymore.."
Now that bandwidth is just going to be even more restricted, but then again, it hasn't stopped Intel, as they have a 4x PCIe 3.0 interconnect between the CPU and the chipset as well, they just called it a fancy name (DMI) to make it sound like it was something special.
When it comes to these chipsets, a PCIe switch would be used to "make" more PCIe lanes, but the bandwidth between the chipset and the CPU is still limited, both for AMD and Intel.
It doesn't appear to limit performance in most cases though, as otherwise Intel boards with NVMe drives connected via the chipset in the case of Intel boards, wouldn't perform as well as they do.
16/4/4 is what we have now. That's PCI-E slots, m.2 slot and chipset. Using a switch is a neat way to split lanes but you don't get anymore bandwidth. If you hook up a bunch of NVMe drives to the Intel chipset and hammer them, you'll be bottlenecked pretty quickly. AMD took the simple approach of saying you'll need more than 4 lanes for peripherals so you'll only get gen 2 speeds but you'll be guaranteed the full speed at all times. It's two different approaches. There's a trade-off either way. Considering the lanes we see in higher end AMD chips there should be untapped potential for mainstream chips.Yes but are you getting Threadripper levels of bandwidth from your Broadcom chip that splits that x4 link or will that triple SLI setup get choked? Or will your 4 NVMe drive RAID array be able to run full tilt on your DMI link?
Don't get me wrong. We need more lanes and sometimes (or even most of the time) a switch is a great solution but it would be disingenuous to call it 24 lanes of PCI-E 3.0 because if you're going to use all those lanes simultaneously then you have a bandwidth problem so it relies on peripherals not needing full bandwidth all the time. It gives you a whole lot of freedom but it isn't perfect and I don't find AMD's approach to be bad either. It's more straight forward in a wysiwyg kind of way. I'm sure the choice to go that route was a combination of cost and outsourcing chipset design but it works though.