Wednesday, September 9th 2020
AMD Announces a Red October: Zen 3 on October 8, RDNA2 on October 28
AMD CEO Dr Lisa Su on Twitter just announced AMD's next-generation Ryzen processors based on the "Zen 3" microarchitecture, and next-generation Radeon RX graphics cards based on the RDNA2 graphics architecture. AMD is promising a "red" October, with next-generation Ryzen "Zen 3" launch on October 8, and next-generation Radeon RDNA2 launch on October 28. We know for sure that AMD is referring to Ryzen and not EPYC, looking at the Socket AM4 MCM animation being used. The teaser picture for Radeon RDNA2 also hints at a new reference cooling solution with large axial fans.
Update 16:54 UTC: In a separate Tweet, AMD announced the Radeon RX 6000 series graphics cards, based on the "breakthrough" RDNA2 graphics architecture.
Sources:
Dr Lisa Su (Twitter), Radeon RX (Twitter)
Update 16:54 UTC: In a separate Tweet, AMD announced the Radeon RX 6000 series graphics cards, based on the "breakthrough" RDNA2 graphics architecture.
141 Comments on AMD Announces a Red October: Zen 3 on October 8, RDNA2 on October 28
- nVidia fans that wouldn't buy AMD anyway
- overhyped people that aren't even waiting for Ampere reviews (much less RDNA2)
- (early) buyers that always get the most expensive alternative anyway without second thought (usually still top end nVidia buyers)
- the ones that already sold their massively devalued 2080Ti 's, and are now desperate for a new card (tough luck...)
- people that urgently will need a new GPU by those weeks, because theirs just broke (which just happens during the entire year, so cases are limited)
All the rest, the minimally patient buyer, is waiting for one or more of the following:
- Ampere reviews (both vanilla and several custom partner models) (regardless of being neutral or exclusively nvidia buyer) (and some might not even be convinced by stuff like TDP, etc...)
- Ampere prices and stocks to stabilize (and in the meanwhile check reviews and decide what are the best models to aim for)
- RDNA2 reviews (both vanilla and several custom partner models) (to see if it's a better choice than Ampere)
- RDNA2 prices and stocks to stabilize (and in the meanwhile check reviews and decide what are the best models to aim for)
In conclusion: most people will want to wait and see how all the GPUs perform, check all the cards, make a better level-headed choice of specific models, and also get a "non price inflated" custom partner card, regardless of being Ampere or RDNA2. That means: they won't even bother with the holiday season, they're buying well inside Q1 2021.... so AMD announcing/launching RDNA2 several weeks after nVidia in October2020 makes zero difference. It would make a LOT of difference it AMD had nothing to release for another 6 months. But in this case in particular? Not really. They only need to have a good line up... if it performs well, it will sell well through 2021... because that's what most people do: get stuff that is competitive and a good deal for what they need. If RDNA2 ends ups sucking in reviews, then at least they'll be even more comfortable in buying an Ampere at a fair price in 2021 and laugh at all the jump starters.
As for Nvidia fans, I don't know the population, but I reckon most people are brand agnostic. The only reason why they are flocking to Nvidia is because there are not strong product lineup at the high end. In the mid end, the RX 5700 and 5600 offers very good value, but marred by unstable drivers for quite a long time which is also driving people towards Nvidia since there is no other alternatives.
I agree that most people will wait out since they don't really upgrade as often until they see a good deal. But what AMD will be losing out is the initial few batches of people upgrading not just from a monetary perspective, but also from a market share perspective. Missing half the holiday seasons will also mean losing a sizeable chunk of sales. That is the reason most companies release new products by Sep.
They need to get some numbers "COUGH" honest ones too. I want facts not just the typical BS they been throwing around. No not in all cases, if AMD stay silent fuck it i will most likely get a nVidia card. Although still thinking if i should bother still at all but leaning more of just picking up a 3070 and have done with it.
Context!
32bit operands? Sure, rock-solid throughput of 6 cycles for consecutive instructions > 1/6 DIV per cycle (xxx Lake uarch).
What about 64bit operands? Well, sides reverse don't they? (I assume) Micro-coded calculation, variable latency & variable throughput, twice slower than Zen2. What is even more intriguing, slower than Goldmond Plus uarch which does not spot fancy fixed 6cycle reciprocal throughput for operands shorter than 64bits!
PDEP/PEXT
GPR scatter-gather niche? Sure Intel created those instructions (BMI2), if they would be "micro-coded" on their flagship uarch, then I don't see a reason for even making them.
Differences between capabilities of ALUs of Intel and AMD architectures (not counting front-end, cache & memory) are much bigger than many "IPC" discussions admit.
What about POPCNT/LZCNT/TZCNT? (number of bits set to 1, number of leading zeroes, number of trailing zeroes - simple explanation for those, who are "not in the know")
Latency in Lake uarch is 3, AMD 1 (or 2 for TZ). That is not all. On Intel only a single port is capable of handling these instructions (throughput is 1 instruction per cycle). On AMD? All four ALUs are able to execute POP and LZ instructions (4 "IPC") and 2 TZ instructions & 2 "IPC".
There is one more implication based on the differences of Intel "Super-ALUs" vs. AMD clustered ALUs and separate GPR & SIMD "engines". By executing these three instructions you block port1 which is really an abstraction of a "super ALU" (take a look at en.wikichip.org/wiki/intel/microarchitectures/coffee_lake what else it is supposed to handle).
AMD design philosophy of a separate "vector engine" means, that they do not block each other (see en.wikichip.org/wiki/amd/microarchitectures/zen_2 ).
Which I suppose is the reason why AMD sees higher gains when SMT is enabled as there is no way to utilize such wide engine in a single thread / one non-artificial instruction stream.
[/END of OT]
I am looking forward to Zen3 mostly because of unified L3 cache. At least in Azure, Zen2 CCX are exposed as NUMA nodes (starting with 16 "virtual core"/thread VMs) to let those not intimate with the details know, that spreading threads across all cores will randomly end up with cache misses even if you expect, from the code perspective, that it "should" be present in the cache.
Cache-sensitive workloads see actually higher perf degradation (vs theoretical *2) on Zen2 than on Cascade Lake when you double the size of VMs (from 4c/8t to 8c/16t).
AMD RDNA2 launch event in 7 weeks or a month and half, oh the horror. :kookoo:
Still i'm wating for Zen3, but i'll most likely wait for it till Zen4 releases. :D Also with the increased mid range prices over the years, i'll wait a lot more with RDNA2 or with nv's Ampere.
For AMD every day matters considering people are already heavily hyped for Ampere.
So they either launch in that two weak time frame (Oct. 28.-Nov. 01.) with at least one SKU being available in retail / etail or there will be a lot of upset people and the proverbial ball had been dropped again.
Currently they are not a year but only 1-2 months behind big green in product cycle and that is not as bad as you make it out to be. But honestly they had lost tremendous mindshare in the past years with overhyped releases that "failed to deliver" in one way or another and then came the driver debacle with NAVI cards that were amplified by the release of the new 2020 software suite.
Honestly I wouldn't even mind if they would release only in December but have a rock stable driver stack / software suite with all the bells and whistles working as they should for RDNA2. Cause in the end no matter how long those bars in the charts are, when people question their own decisions to buy the product due to software issues.
Spoiled for offtopic:
I've played around with it for a weekend. I found other good uses of PEXT and PDEP: not just in bitfields but also Hashing (PDEP / PEXT can really "mix up the bits"). I really think that PDEP / PEXT are the most "creative" new instructions in recent memory. I'm betting you got it reversed by the way. TZCNT is equivalent to popcnt((x & -x) - 1), which means the TZCNT instruction can recycle the adder and negation circuits on a CPU. LZCNT on the other hand, cannot be emulated quickly by any standard CPU.
POPCNT: That's cool and I wasn't aware of this fact. POPCNT is one of my favorite instructions.
TZCNT As stated earlier: TZCNT is popcnt((x & (-x)) - 1), which is 400% slower than a dedicated instruction (but still very fast at 1x popcnt((x & (-x)) - 1) per clocktick bandwidth on Zen processors: 4-instructions on 4 pipelines, that can almost certainly be out-of-order scheduled pretty finely).
LZCNT: Okay, that's nifty. Can't be replicated quickly on any machine. I fortunately haven't had the need for LZCNT (Given the efficiency of TZCNT, I "favor" the TZCNT direction heavily whenever I'm playing with bitsets).
Fun fact: POPCNT, TZCNT, and LZCNT are efficiently executed on NVidia and AMD GPUs. So learning to use these instructions is great for GPU programming. And GPUs are surprisingly good at 32-bit integer bitset operations, thanks to single-cycle implementations of these instructions.
Ps5 comes first for me though :ohwell:
Actually Amd IPC is higher.