Monday, May 31st 2021
AMD "Zen 3+" Microarchitecture is "Zen 3" with 3D Vertical Cache Technology, 15% Gaming Perf Gain
AMD CEO Dr Lisa Su, in her Computex 2021 Keynote address detailed what could very well be the "Zen 3+" microarchitecture that's been in the news lately, although the name "Zen 3+" was never used in the keynote address. AMD has collaborated with TSMC on developing a new die-on-die 3D stacking technology using TSVs (through-silicon vias) and structural silicon substrate, to place a 64 MB SRAM on top of the "Zen 3" CCD, which it calls 3D Vertical Cache. This cache die sits directly over the region that has the CCD's own 32 MB L3 cache, and the difference in height between the two dies is leveled using structural silicon. At this point we don't know how the cache hierarchy is changed, whether the 64 MB add-on cache is contiguous with the on-die L3 cache, or whether it's an L4 victim cache to the L3$. With it, the total cache amount of the CCD jumps to 100 MB (4 MB L2 caches + 32 MB L3 cache + 64 MB 3D Vertical Cache).
AMD has made some startling claims as to the performance impact of 3D Vertical Cache Technology. It claims that gaming performance improves by an average of 15%, which is akin to a generational performance impact in and of itself. With these gains, AMD hopes to make up whatever gaming performance deficit the "Zen 3" microarchitecture has against Intel's "Rocket Lake-S." The first processors implementing 3D Vertical Cache Technology will start arriving by the end of 2021, which means it could very well be the Ryzen 6000 series desktop processors, leaving the Ryzen 7000 series to be based on the 5 nm "Zen 4," on track to a 2022 release.How AMD plans to release these updated dies on the client ecosystem remains a mystery. The prototype Dr Su showed in her keynote address clearly appears to be Socket AM4. If the new Socket AM5 is on course to later this year, it's very likely that these "Zen 3 + 3D VC" CCDs could be paired with an updated cIOD (client I/O die) that supports DDR5 memory, and packaged for AM5.
AMD has made some startling claims as to the performance impact of 3D Vertical Cache Technology. It claims that gaming performance improves by an average of 15%, which is akin to a generational performance impact in and of itself. With these gains, AMD hopes to make up whatever gaming performance deficit the "Zen 3" microarchitecture has against Intel's "Rocket Lake-S." The first processors implementing 3D Vertical Cache Technology will start arriving by the end of 2021, which means it could very well be the Ryzen 6000 series desktop processors, leaving the Ryzen 7000 series to be based on the 5 nm "Zen 4," on track to a 2022 release.How AMD plans to release these updated dies on the client ecosystem remains a mystery. The prototype Dr Su showed in her keynote address clearly appears to be Socket AM4. If the new Socket AM5 is on course to later this year, it's very likely that these "Zen 3 + 3D VC" CCDs could be paired with an updated cIOD (client I/O die) that supports DDR5 memory, and packaged for AM5.
56 Comments on AMD "Zen 3+" Microarchitecture is "Zen 3" with 3D Vertical Cache Technology, 15% Gaming Perf Gain
Also, this comes to mind.
METHOD AND APPARATUS FOR VIRTUALIZING THE MICRO-OP CACHE
If you look at only the SRAM, it's only a portion of the actual space, maybe they reuse the same L3 control and tags.
I suspect the SRAM top top spread over the L2 cache of each core too.
As per Andreas Schilling on Twitter that spoke with AMD.
- Zen 3 was made with that in mind. No modification needed.
- it's 1 layer of 64 MB of cache
- It actually expend the level 3 cache. With minimal latency increase.
Based on that and the picture above I suspect the 64 MB is way denser than the 32 MB bellow. I suspect the L3 control and L3 tags support also the SRAM in the the V Cache.
Also caches scale in frequency with the clock speed of the CPU, running the cores at something like 800mhz will of course result in dramatically less heat output from the caches.
However, there's that interesting bit in the illustration, "direct copper-to-copper bond" between the two dies. "Copper" should be the top metal layer, so the dies are bonded top-to-top. Looks clever ... but it also means that, firstly, AMD would have to NOT use flip-chip die bonding, contrary to regular Ryzens and other modern CPUs. To make it work, they'd have to make a version of substrate with much different (mirrored) wire routing. Secondly, TSVs would not be needed for "silicon-to-silicon communication" but for CCD-to-package substrate connections.
I must be missing something here. @FritzchensFritz ... ah damn, he's not a TPU forum member.
Chasing the absolute highest performance numbers only leads to disappointment. They're only the 'best' for six months to a year.
Until August of last year I was using a 2700k from 2012 - it was chuggin' along just fine.
With a 3080 (before it died and i got the 3090) there was a good 30-40FPS gain every gen with ryzen, as i tested it with all the systems in the house for the lulz
That said, i game at 165Hz - those gains at max FPS are meaningless, if you dont have the high refresh monitor and high powered GPU to benefit from it.
5600x is my absolute happy recommendation for a max FPS gaming chip this gen, so stupidly fast without the 5800x heat issues at all core load.