Great, now just use a single stack for zen4/5 based APU or even CPU's after which Intel will probably through in the towel :nutkick:

There is also up to 920GB/s per stack. That mean 3.68TB/s with 4 stacks.
www.innosilicon.com/html/ip-solution/39.html

This is what I would love in a Nano GFX card. ...Lets see if GDDR6x can responded to those speed.

delshayThis is what I would love in a Nano GFX card. ...Lets see if GDDR6x can responded to those speed.

GDDR6X is not person. It not has response.

R0H1TGreat, now just use a single stack for zen4/5 based APU or even CPU's after which Intel will probably through in the towel :nutkick:

You know, I've ALWAYS wanted a powerhouse APU, something akin to the amount of CUs in the Xbox Series X Soc, but with 8GB of HBM2e integrated into the Soc. I think these will eventually come, but I think the major hurdle is a consumer one. What I mean by that, is that the vast majority of buyers want to be able to independently upgrade their CPU, GPU and system memory, so an Soc that ties you to a locked combo probably wouldn't be that widely popular on the DIY market. They would make epic SFF builds though.

Personaly, I wouldn't care if such APUs required a package the size of threadripper, but I realize I don't represent the majority.

Those 240,000 wafers weren't defective after all, they were radioactivated and destined to become HBM3, but were then sent out to customers in confusion due to shortages and Covid.

pointless, until radeon/geforce build cards with this many speed it's only will be for computational cards 5000$ and higher, it sad becuase this speed is need for ray trace performance :x

R0H1TGreat, now just use a single stack for zen4/5 based APU or even CPU's after which Intel will probably through in the towel :nutkick:

The main idea of an APU is a low cost CPU+GPU solution. HBM main issue is that to have it you must use an expensive Silicon interposer.

So we won't see any APU+HBM for consumers anytime soon, but if the server/HPC market demand such product to justify it's cost then they will do it, but it seems there's not enough demand because we still don't have such product even for the HPC market.

Maybe with the current advances in packaging technology this might be possible, like if it will be possible to 3D stack the HBM stack over the IO die or over the cache just like how AMD's 3D V-Cache works. The main issue with such implementation is the Z-Height, HBM are already a 3D stacked DRAM dies, so they're "tall" if we can say that, stacking them over the IO/Cache will make the main Core die have lower Z-Height.
Intel was faced with this issue with their strange Intel+Radeon opGPU as it uses HBM also (connected via EMIB), they did some engineering work and succeeded but the concept was costly and never got popular enough, they dropped it.