ValantarCurrent APUs are actually pretty decent, though obviously you can't expect 1080p high or ultra in anything demanding. I recently saw a "leak" (to be taken with the requisite amount of salt, obviously) of a possible Rembrandt/ 6000-series AMD APU (8c8t Z3, unknown no. of RDNA2 CUs) scoring 2700 in Time Spy, placing it ~200 points ahead of a 1050 Ti and ~600 points behind a 1650. Now, a 1650 is hardly a powerful GPU, but an APU beating a 1050 Ti is still pretty good, and a significant improvement over current APUs. Looking forward to seeing what DDR5 and RDNA2 brings to APUs.

That's a good indication of purposeful stagnation. It's almost 2022, and the most we get is a promise of having 1050Ti-level performance, while over 3 years ago we had glimpses of what's possible with i7-8809G or custom Zen+ in Subor Z+. Both had a GTX1060/RX470 level of performance, which is still good enough for 1080p gaming at adequate quality settings. With advances in graphics, and with super-resolution in picture it's more than feasible, and there's a huge demand for it on the market.

ValantarYou're not entirely wrong, but you can't discount the effect of slow GDDR on CPU performance either. CPUs need latency more than bandwidth, so GDDR for a CPU is just begging for a performance loss. IMO that's as much of the fault for the poor CPU performance as the smaller caches - remember, the mobile/desktop APUs have similarly small caches and perform well still.

Ah yes, I'd completely forgotten about that - In addition to the hamstrung PCIe bandwidth, TDP limitation, and clockspeed disadvantage, the high latency GDDR wouldn't be helping and I'm going to assume that the silicon's IMC only has support for GDDR6 so there's no option to use DDR4.

silentbogoThat's a good indication of purposeful stagnation. It's almost 2022, and the most we get is a promise of having 1050Ti-level performance, while over 3 years ago we had glimpses of what's possible with i7-8809G or custom Zen+ in Subor Z+. Both had a GTX1060/RX470 level of performance, which is still good enough for 1080p gaming at adequate quality settings. With advances in graphics, and with super-resolution in picture it's more than feasible, and there's a huge demand for it on the market.

Is it indicative of purposeful stagnation, though? The Subor Z+ has a custom motherboard with onboard GDDR5, and KBL-G has HBM. Custom DIY desktop motherboards with onboard RAM will never, ever be a sane business decision, and thus won't happen. Even with the advent of DDR5, there are limits to how many CUs you can feed over a 128-bit interface. AMD clearly found that 8 high clocked Vega CUs was as high as there was a point to going with DDR4 (which is supported by how well these APUs scale with RAM overclocking). That's with DDR4-3200 as a baseline. Assuming a move to JEDEC DDR5, DDR5-4800 (which is a likely baseline for laptops and OEM systems for the first generation at least) would represent exactly the same bandwidth/CU/clock speed for a 12CU APU as DDR4-3200 for an 8CU one. I have no idea how the change from Vega to RDNA2 will affect that (if anything, I expect the increased architectural efficiency to increase DRAM bandwidth pressure), but assuming no change in that or clock speeds, 12CUs is about as high as they can reasonably go without increasing the DRAM bottleneck.

Now, I would absolutely love to see a 20+CU APU, and I hope we will in the not too distant future, but given the die space requirements that would necessitate AMD moving to a 2-die or MCM strategy, and so far they've never had more than 1 die, and no MCM APUs - likely for cost reasons. A new monolithic die would be both large and relatively niche, so it would also be expensive, and if it's still held back by RAM bandwidth (and to a disproportionate amount compared to lower CU count APUs) then it might simply not make sense unless they also add something like HBM, which would drive up prices even further. I agree that KBL-G was a great concept, though the execution was a bit so-so - but it was also, crucially, only possible due to Intel's EMIB. It's only in recent months that TSMC has been able to deliver its equivalent (LSI) at scale. So until recently AMD has been unable to even manufacture something equivalent to KBL-G without going for a full GPU interposer, which gets very expensive. And for an MCM solution, there's a significant problem of fitting an 8c CCD, an IOD, a ... GCD?, and a stack of HBM on an AM4-sized substrate, again limiting them to DDR5 bandwidth My dream APU has ~20CUs, 4GB of HBM, 6-8 cores, and it could have a stripped-down IOD if that helps things. But that's still an expensive proposition, which makes it a very niche product. I am really, really hopeful that AMD's future MCM GPUs will have their smallest die designed to also act as an APU GCD to enable more flexible APU designs, but I think we're still a few generations out from that. And until then, this is looking pretty decent.

How feasible would it be to merge the IOD with the IGPD? Ie, there'd be compute dies much like the current non-IGP Ryzens, then an IO/IGP die, potentially w/ stripped down IO. Then you can also make parts w/ the same core config, better IO w/ pure IOD, or one w/ the IO/IGP die

not sure how feasible/economical that'd be tho

ValantarNow, I would absolutely love to see a 20+CU APU, and I hope we will in the not too distant future, but given the die space requirements that would necessitate AMD moving to a 2-die or MCM strategy, and so far they've never had more than 1 die, and no MCM APUs - likely for cost reasons. A new monolithic die would be both large and relatively niche, so it would also be expensive, and if it's still held back by RAM bandwidth (and to a disproportionate amount compared to lower CU count APUs) then it might simply not make sense unless they also add something like HBM, which would drive up prices even further.

I've been shouting for more CUs in AMD's APUs for years now, and the naysayers have always said it's pointless because DDR4 RAM bandwidth was the limiting factor. DDR5 is here, lets see at least 12CU solutions as the default in silicon please - the extra four CUs really don't use much die space compared to the cache and the cores.

As for larger CU solutions, perhaps MCM is the way to go - rather than modifying the Zen3/Zen4 CCD die, why not make an I/O die with an additional 16CU or 24CU IGP on it? It's one step closer to the all-important IMC and it's likely cheaper than designing a large monolithic die. Ultra mobile parts can still get by with the essential IGP on their monolithic die as process node and performance/Watt are still the most vital aspects, but desktops and >25W mobile parts can easily go MCM.

SelayaHow feasible would it be to merge the IOD with the IGPD? Ie, there'd be compute dies much like the current non-IGP Ryzens, then an IO/IGP die, potentially w/ stripped down IO. Then you can also make parts w/ the same core config, better IO w/ pure IOD, or one w/ the IO/IGP die

not sure how feasible/economical that'd be tho

That's an excellent question. There are pretty persistent rumors of future AMD CPUs with iGPUs, which would most likely indicate a small (4CU?) GPU on the IOD. Two challenges with this:
- Current IODs are produced on cheap nodes, both for cost reasons as well as due to I/O generally not scaling well with denser nodes both for power and density. This would likely be fine for a "this has a display output too" iGPU, but not a high performance one. Moving IODs to 7nm or a similar node would make them much more expensive, and with the added GPU they would also likely be quite large (current IODs are pretty huge, after all).
- Layout. With a square CPU package and fixed dimensions, there are limits to how many rectangular chips of a certain size you can fit within it. Fitting a larger IOD with a GPU on board would most likely be really tricky - at least they would need to really succeed in shrinking down the current IOD design, which might entail cutting features. Less PCIe would probably be fine (not as necessary with a powerful iGPU), and you could maybe cut one IF link if these APUs have a maximum of one CCD (with the free space being taken up by HBM) but overall there still isn't that much to cut.

Then again, there are positive things too:
- 5nm CCDs might be smaller, assuming AMD doesn't significantly increase per-core transistor counts for Zen4 (or they make 5nm Zen3 CCDs for APUs?), leaving more space for a bigger IOD w/graphics.
- 2.5D packaging that's cheaper and easier to implement than full-sized interposers might allow them to stack their chips much closer together.

I think this mainly comes down to how much AMD wants to do this, how much they're willing to spend on it, and how many OEM customers they can convince to come on board. If this packaging works for laptops as well, this could sell like hotcakes if AMD got the likes of HP, Acer, Asus and Lenovo on board for entry level APU-only gaming laptops. But if they don't push for it, it won't happen.

Chrispy_I've been shouting for more CUs in AMD's APUs for years now, and the naysayers have always said it's pointless because DDR4 RAM bandwidth was the limiting factor. DDR5 is here, lets see at least 12CU solutions as the default in silicon please - the extra four CUs really don't use much die space compared to the cache and the cores.

Yeah, that's what that leak I linked to indicates. Fingers crossed! I would love my next laptop to be a 12CU+LPDDR5(X?) beast.

Chrispy_As for larger CU solutions, perhaps MCM is the way to go - rather than modifying the Zen3/Zen4 CCD die, why not make an I/O die with an additional 16CU or 24CU IGP on it? It's one step closer to the all-important IMC and it's likely cheaper than designing a large monolithic die. Ultra mobile parts can still get by with the essential IGP on their monolithic die as process node and performance/Watt are still the most vital aspects, but desktops and >25W mobile parts can easily go MCM.

That's my hope. MCM packaging for mobile is tricky due to Z-height (OEMs need their thin laptops!), but hopefully they can get that down to a reasonable level. An IOD that large in a desktop socket will be problematic though - you can't make L-shaped chips, and they need to fit at least one CCD, so there are pretty strict limits to how much larger they can go compared to current IODs. There is room to grow, but not that much - so the main question becomes how much they can shrink the current IOD design if they move to a denser node (considering that IO doesn't scale well), and how much can they cut before people start complaining?

Oh, btw, MCM at 25W might be rather tricky - Infinity Fabric consumes quite a bit of power even at idle and even on 1-CCD CPUs - easily a noticeable amount for a mobile chip, and to a degree that might be a problem for idle power (which needs to go into the 1W range for a competitive modern mobile CPU/APU design. Though they could likely lower this if they used some kind of EMIB-like packaging for the interconnect rather than going through the substrate, or clocked it much lower, but it's not quite as simple as copying current designs, sadly.

If memory serves Zen 4 IODs will be made on 7nm. The only reason why they're still recycling their current anemic 14nm IODs is because they still have an agreement w/ GloFo of purchasing a certain allotment of wafers from them (or something xd).

There's also real incentive of doing this (mobile mostly) because the current 14nm IOD gobbles power like mad. even when it's not really doing anything it consumes like, 20W which is fairly insane

SelayaIf memory serves Zen 4 IODs will be made on 7nm. The only reason why they're still recycling their current anemic 14nm IODs is because they still have an agreement w/ GloFo of purchasing a certain allotment of wafers from them (or something xd).

There's also real incentive of doing this (mobile mostly) because the current 14nm IOD gobbles power like mad. even when it's not really doing anything it consumes like, 20W which is fairly insane

I wonder how much that will improve, seeing how I/O is notorious for not scaling particularly well with node changes - it improves, but nowhere near as well as I/O does. Also, the main power draw in the IOD is likely sadly IF, as that needs to keep 1-2 very high speed links active the entire time the CPU is running, which definitely doesn't come for free.

True enough.

ValantarThe Subor Z+ has a custom motherboard with onboard GDDR5

Dude, not sure if you've noticed, but on today's menu is a custom board with soldered GDDR6.

ValantarIs it indicative of purposeful stagnation, though?

Of course. We have 3 generations and 5 lineups of Zen APUs using the same Vega grapics (which ironically shrinked along with tech process). C'mon, we have octacore ULP chips that outperform 90W desktop CPUs from 4 years ago, we have DDR4 that's nearly twice as fast as back then(and DDR5 hitting the shelves as we speak), but even the good-ole Vega iGPUs keep shrinking and shrinking, while compensating solely by higher clocks. And Navi iGPUs are still nowhere to be seen. AMD will jump straight to Navi2 sometime in this century, but until then the best we've got is bragging that our Vega7/8 beats the living s#$t out of GT1030 D4.

ValantarOh, btw, MCM at 25W might be rather tricky - Infinity Fabric consumes quite a bit of power even at idle and even on 1-CCD CPUs - easily a noticeable amount for a mobile chip, and to a degree that might be a problem for idle power (which needs to go into the 1W range for a competitive modern mobile CPU/APU design. Though they could likely lower this if they used some kind of EMIB-like packaging for the interconnect rather than going through the substrate, or clocked it much lower, but it's not quite as simple as copying current designs, sadly

I said >25W, so basically that means the 45W H-series chips and above for DTR laptops, but yeah I'd forgotten that MCM has higher idle power draw - probably the reason AMD have gone monolithic for all their mobile-focused APUs. I guess that means 12CU is as much as we can hope for then, though with the increased clocks that RDNA2 architecture can achieve, coupled with the improved IPC, it should at least be equivalent to a Vega20, even if AMD doesn't actually make a 20CU part :(

silentbogoDude, not sure if you've noticed, but on today's menu is a custom board with soldered GDDR6.

...and? Let's see: it's using an SoC that literally doesn't have a DDR4 controller (or any other DRAM controller except GDDR6) and thus can't use anything other than GDDR6; it is an SoC that wouldn't work in any existing socket, whether desktop or mobile BGA, and thus necessitates a custom board; it is a board that isn't sold to the general public and doesn't have broad distribution (OEMs and gray market sellers only); it is a product that exists only because AMD are making tens of millions of console SoCs and even at the low, low defect rates of TSMC 7nm there are bound to be heaps of chips that fail to meet spec. So: this is a product born out of either opportunity ("free chips! What do we do with them?") or necessity ("ugh, we have thousands of these dud console chips, we need to put them to use somehow"), either way it is not a product that fits into any other product stack, and a product with very low costs for AMD (as Sony/MS has already bought the wafers; AMD can likely buy back the defects dirt cheap, or have keeping them stipulated as part of the contracts).

The rest of this discussion has been on APUs, presumably for sale to consumers, which must then to some extent fit into AMD's product stack, and must bear the entire R&D cost of its development if it is new silicon. The circumstances of this board and the 4700S vs. the circumstances of a high performance APU would be radically different. And that's why they wouldn't launch an APU like that for DIY retail. Heck, they'd need to design and sell their own motherboards (as they do with this) on top of those R&D costs - so if the chips weren't essentially free like these are, that would be extremely expensive.

silentbogoOf course. We have 3 generations and 5 lineups of Zen APUs using the same Vega grapics (which ironically shrinked along with tech process). C'mon, we have octacore ULP chips that outperform 90W desktop CPUs from 4 years ago, we have DDR4 that's nearly twice as fast as back then(and DDR5 hitting the shelves as we speak), but even the good-ole Vega iGPUs keep shrinking and shrinking, while compensating solely by higher clocks. And Navi iGPUs are still nowhere to be seen. AMD will jump straight to Navi2 sometime in this century, but until then the best we've got is bragging that our Vega7/8 beats the living s#$t out of GT1030 D4.

That's not a valid comparison. CPUs are, in the vast majority of consumer tasks, in no way limited by DRAM bandwidth. So the growth you're describing in CPUs is what happens when nothing else is holding you back and you have major architectural improvements. GPUs, on the other hand, are essentially always DRAM bandwidth limited. Hence why there's little point to sticking a bigger iGPU on something if you can't keep it fed. And yeah, I also think it's a bit odd that they're still using Vega, but given how it performs, I don't mind. It was probably cheaper, easier, and saved them the headache of either designing a tiny RDNA1 chip or really rushing an RDNA2 design for current APUs. It's probably down to cost savings (or at least investing less) in the end, but I doubt there is something tangibly better that they could have given us up until now. Seeing Vega live on in APUs till 2021 is indeed odd, but it performs fine for what it is, and without DDR5 RDNA(2) likely wouldn't have given us much more performance anyhow.

Also, remember that while we have faster DDR4 today than 3-4 years back, APUs are (and will always be) mobile-first, and in mobile, JEDEC is the name of the game. Mobile RAM tops out at 3200C22 or C20 or something. That's faster than the 2133, 2400 and 2666 of a few years back, but not even close to enough to matter much. And Vega at 2x the speed is more than capable of making use of that increase.