Saturday, October 26th 2024
AMD Ryzen 7 9800X3D Has the CCD on Top of the 3D V-cache Die, Not Under it
Much of the Ryzen 7 9800X3D teaser material from AMD had the recurring buzzwords "X3D Reimagined," causing us to speculate what it could be. 9550pro, a reliable source with hardware leaks, says that AMD has redesigned the way the CPU complex die (CCD) and 3D V-cache die (L3D) are stacked together. In past generations of X3D processors, such as the 5800X3D "Vermeer-X" and the 7800X3D "Raphael-X," the L3D is stacked on top of the CCD. It would stack above the central region of the CCD that has the on-die 32 MB L3 cache, while blocks of structural silicon would be placed on top of the edges of the CCD that have the CPU cores, with these structural silicon blocks performing the crucial task of transferring heat from the CPU cores to the IHS above. This is about to change.
If the leaks are right, AMD has inverted the CCD-L3D stack with the 9000X3D series such that the "Zen 5" CCD is now on top, the L3D is below it, under the central region of the CCD. The CPU cores now dissipate heat to the IHS as they do on regular 9000 series processors without the 3D V-cache technology. The way we imagine they achieved this is by enlarging the L3D to align with the size of the CCD, and serve as a kind of "base tile." The L3D would have to be peppered with TSVs that connect the CCD to the fiberglass substrate below. We know where AMD is going with this in the future. Right now, the L3D "base tile" contains the 64 MB 3D V-cache that gets appended to the 32 MB on-die L3 cache, but in the future (probably with "Zen 6"), AMD could design the CCDs with TSVs even for the per-core L2 caches.
This piece of speculation also perfectly explains what "X3D boost" could be. With the CCD making direct contact with the IHS the way it is in non-X3D processors, the X3D processors could have the same overclocking capabilities as the regular chips. There are much fewer thermal hurdles in the way, and AMD can go ahead and give these chips the same TDP and PPT values as regular chips, as well as higher clock speeds. The company used to be conservative with the PPT and clock speeds of its X3D processors in the past.
AMD is expected to launch the Ryzen 7 9800X3D on November 7, 2024.
Source:
HXL (Twitter)
If the leaks are right, AMD has inverted the CCD-L3D stack with the 9000X3D series such that the "Zen 5" CCD is now on top, the L3D is below it, under the central region of the CCD. The CPU cores now dissipate heat to the IHS as they do on regular 9000 series processors without the 3D V-cache technology. The way we imagine they achieved this is by enlarging the L3D to align with the size of the CCD, and serve as a kind of "base tile." The L3D would have to be peppered with TSVs that connect the CCD to the fiberglass substrate below. We know where AMD is going with this in the future. Right now, the L3D "base tile" contains the 64 MB 3D V-cache that gets appended to the 32 MB on-die L3 cache, but in the future (probably with "Zen 6"), AMD could design the CCDs with TSVs even for the per-core L2 caches.
AMD is expected to launch the Ryzen 7 9800X3D on November 7, 2024.
110 Comments on AMD Ryzen 7 9800X3D Has the CCD on Top of the 3D V-cache Die, Not Under it
Otherwise I would prefer to not pay extra for some useless feature (for me, just to be clear).
The only obstacle is really intel not putting forward competing products to entice this, luckily the increasing market share from Apple and the threat from Qualcomm and Windows on ARM will keep them motivated.
For these reasons I think they might be planning something even crazier. They might be able tackle both of these problems by putting L3 cache on both sides! :laugh:
This way they'd have enough area for same sized L3 and since they can connect it from both sides number of interconnections doubles which solves the bandwidth problem.
This wouldn't help with the IHS and core contact problem but it shouldnt be much of a deal this time around. 105w power limit and cores with larger die area (larger than 7000 series) it should perform at least as good as 9700x in multicore scenarios by default anyway. This would also explain why AMD wanted a 65w 9700x. Now their 3D chip wouldn't look slower in any scenario compared to non 3d counterpart (except maybe single core).
Edit: This setup would also help to increase the L3 cache. 128MB would be a stretch but 96MB should be pretty possible.
This alleviates that IU suppose but there's no extra cacheEconomically not viable especially considering the performance uplift will be minimal
Fabric trough memory might become a thing though
Well the socket might still be OK but the PCB is to small