Tuesday, October 29th 2024
De-Lidded Ryzen 7 9800X3D Pic Confirms 3D V-cache Die Moved Below the CCD
The upcoming AMD Ryzen 7 9800X3D processor is already in the hands of hardware modders, who have put the chip through de-lidding (removal of the integrated heatspreader or IHS), revealing what's underneath. In the 9800X3D de-lidded picture, the CCD appears plain, with no apparent L3D on top, unlike on the 7800X3D (second picture, below). We'd been hearing reports that with the 9000X3D series, AMD has redesigned the way the 3D V-cache die (L3D) and the CPU complex die (CCD) are stacked together, by inverting their arrangement, such that the CCD is on top, and the L3D below.
In past generations of X3D processors, such as the 7800X3D and the 5800X3D, the L3D is stacked on top of the CCD, with structural silicon handling the crucial task of transferring heat from the CPU cores to the IHS. This inversion in stacking should ensure better thermals for the CPU cores, the 9800X3D boosting behavior should be similar to that of non-X3D chips, such as the 9700X. AMD has given the 9800X3D a 120 W TDP and 5.20 GHz boost frequency. This inversion of the CCD and L3D stacking is probably what is behind the "X3D Reimagined" teaser blurb by AMD.
Source:
Wccftech
In past generations of X3D processors, such as the 7800X3D and the 5800X3D, the L3D is stacked on top of the CCD, with structural silicon handling the crucial task of transferring heat from the CPU cores to the IHS. This inversion in stacking should ensure better thermals for the CPU cores, the 9800X3D boosting behavior should be similar to that of non-X3D chips, such as the 9700X. AMD has given the 9800X3D a 120 W TDP and 5.20 GHz boost frequency. This inversion of the CCD and L3D stacking is probably what is behind the "X3D Reimagined" teaser blurb by AMD.
32 Comments on De-Lidded Ryzen 7 9800X3D Pic Confirms 3D V-cache Die Moved Below the CCD
Dunno about Vcore though (which the N5 regular CCDs relied on to max boost clock), still need to find a way to decouple Vcore from cache voltage to enable the same on X3D? 5.2GHz is hardly a huge bump like some sources have been describing.
We're not there yet, but if there is now less impact on frequencies due to heat transfer, there should be less downsides compared to regular Ryzens in productivity workloads.
We might see some overclocking this time around, but I'm sure it'll be extremely limited.
Intel's new DLVR enables per-Pcore and per-cluster Ecore voltage, as well as separate L3. Who knows if AMD will go the same way.
But the difference could also lie in the 9800X3D being able to hit 5250 out of the box, which 7800X3D doesn't consistently do without CO persuasion. Guess we'll see in due time
I'm pretty sure that back in the day, the official line from AMD regarding Vcache was regarding its [feared] fragility under high Vcore and not temps, which led to them being scaled back so much. Since L3 doesn't generate much heat at all so that's not a concern now, separate voltage rail for L3 a la Arrow Lake could allow the freq gap to further close.
But I also don't see why AMD would want to clock X3D that high. Would stop them from being able to milk the non-X3D parts, since they would not survive without a price cut.
I checked the source and both his channels but can't see anything, what am I missing..
Anyone can buy his delidder.
On that note, I plan to delid a 9950X3D to add LM, that will be fun, hope I get a high clocking bin
I wonder how many 1851 heaters he will sell..Roman have showed on youtube that it works with 7000/8000/9000.