Friday, June 29th 2007
AMD Native x86 Quad-Cores Shipping In August
AMD announced today that Quad-Core AMD Opteron processors, code-named "Barcelona," are planned for shipment in both standard and low power versions at launch later this summer. This would be the first time AMD has made both standard and low power parts immediately available as part of a new processor launch.
During this first launch, processor speeds are expected to be available up to 2.0 GHz.
Source:
AMD.com
During this first launch, processor speeds are expected to be available up to 2.0 GHz.
59 Comments on AMD Native x86 Quad-Cores Shipping In August
No.
Is a barcelona going to necessarily be the same?
No.
Remember how AMD originally wanted to seperate socket 940 from 754?
What makes you think they wont? Intel did.
the Xeon has QUAD CHANNEL DDR2.
The core 2 duo does NOT.
The arena is like comparing a nascar car to an F1 car.
They are different.
besides, you aren't actually "comparing" the CPU's because theres no performance data anywhere in this thread.
This it should remain, a server CPU argument, because its in no way shape or form related to the desktop as no specifications about the CPU are known other than a clockspeed.
Chances are a dual dual core Xeon is going to stomp a core 4 quad desktop CPU.
Next to that, we're not talking about a small difference, we're talking about a completely different infrastructure, Tigerton will utilize CSI instead of the current FSB, it has many interlinks to handle the bandwidth for the 16 cores these beasts will initially house. Look at IBM's X4 chipset for example. IBM you say? Yes, IBM makes chipsets for these kind of systems, completely different league.
Long story short, wait for both platforms to appear, then see how they perform, forget about C2D and Xeon DP's here.
You can't multi-CPU those? ;)
Last I checked, woodcrest and clovertown were core based :)
store.apple.com/AppleStore/WebObjects/BizCustom.woa/6314008/wo/pM1dOnyABbdT2o6HAd01fYl1Geu/1.?p=0
Anything 4+ is really not a concern for 99% of the population here xD
However, the dual CPU argument remains the same. Its different.
Xeon MP = Xeon Multi Processor, 7000 series
Has been like that since the first Xeons, they're 2 completely different markets. Same with the Opterons, 1xx, 2xx and 8xx.
Thats insanely retarded. I figured that would be one of the first places they would want to stick the suckers.
First of all,Barcelona is a K10 server part that fits in both Socket F and SocketF+(split power planes) with only the BIOS update(info directly from AMD!!).So it's backwards compatible with ANY socket F motherboard for dual core Opterons currently shipping(RevF stepping).Second ,Barcelona is K10 chip with HyperTransport 1.0 support,not HT3.0.Barcelona is coming in August with speeds up to 2Ghz,with Tier 1 suppliers having the systems in September.Both standard and HE(low power ,68W) versions will be available.
The HT3.0 K10 chip is codenamed Budapest and will come in late Q3,early Q4 and will be a workstation MPU,for uniprocessor systems( UP).It will fit in ANY AM2 or AM2+(split power planes) with only a BIOS update!!So it's not a desktop CPU,but will work regardless of that in any desktop mobo(provided the BIOS is available).
Phenom is Ht3.0 desktop part which comes in November and is basically identical to Budapest and Barcelona(only the Barcelona has HT1.0).Chip has all the features of K10 core arch(improved OoO,32 byte instruction fetch ,L3 cache,improved mem. contrl with prefetch function,L1 direct prefetching,doubled L1 bandwidth,128bit FPU/SSE,SSE4A instruction set,increased number of fast path(direct path) instructions etc.)
Phenom will wit in ANY AM2 or AM2+(split power planes) with only a BIOS update needed.
All K10 CPUs have DDR2 integrated mem. controller with support for DDR2 memory(rumor has it that they do support DDR3 also,but still just a rumor).All K10 CPus,when ran in AM2+ mobo can clock independently the mem. controller from the CPU cores.So meme .controller has it's own PLL and can work on higher or lower freq.This will have a large impact on OCing,since the mem. controller has its own voltage plane and can work on less volts and less freq. than the cores themselves.
All K10 CPUs have much better power saving features than K8(and Conroe,Penryn).This will allow K10 to be the most power efficient CPU on the market.
All K10 CPUs will receive a die shrink to 45nm with some arch. improvements in Q3 2008,and will be a competitors to intels Nehalem.All this K10.5(shrank) CPUs will have increased L2&L3 caches,SSE4(full subset) and other improvements to SSE and ALU engines(to help them compete better with nehalem)
I just wanted to post this information since i saw that too many people on this board really don't have correct informations about K10 and motherboard support for it,so i wanted to clear up some things.
I must say that these specs are correct and not just some speculation.
Hope this info helps clear the confusion around the mighty K10 ;)
Regards
inf
But I'm curious as to where you got info :) :eek:
I'm pretty sure most of those were announced in the past, but theres just no benchmark information at hand, so we really can't conclude much for performance.
It sure sounds like its got some extra muscle coming, but it needs to hurry or its going to be competing with even more muscle from intel...
Yeah,i registered here since i couldn't believe my eyes when i read some posts :(.I thought people here knew more about K10,but lets hope it all changes since K10 is practically 1.5 months away from public demonstration.
PS Info was from various friends ;) and from public(Ace's hardware forum) and Analyst day papers.Also those pesky little patents at US patent office could get handy :).
A lot of the old info is just..... old.
If its true, they probably won't be changing a ton as right now I would imagine they're working on getting it made..
And there is no "if it's true".No if at all.
L3 is one major arch . improvement AMD made when they designed K10.Although it isn't the greatest of all ,it is the one that people get stuck on when they read the specs on the newegg :D.And it will bring a lot in multithreaded apps and multitasking environments.
Aren't they sharing this like Intel does, though?
Its not so much the addition of L3, but more so the implementation.
Happen to have any CPU diagrams laying around? :D
I'd really like to see how its laid out in comparison to the K8 currently.
Here ya go:
chip-architect.com/news/2007_02_19_Various_Images.html (all cores from K8 to K10,Conroe and Penryn included)
Here is a K10 core(without Mem. controller and L3) overview diagram:
Here is a die plot(all parts included):
Win. :)
Looks like we should see a significant improvement with ddr2, alone.
www.realworldtech.com/includes/templates/articles.cfm?ArticleID=RWT051607033728&mode=print
?
:p
From my link above.