Tuesday, June 16th 2009
GLOBALFOUNDRIES Details Advanced Technology Aimed at 22 nm and Beyond
GLOBALFOUNDRIES today described an innovative technology that could overcome one of the key hurdles to advancing high-k metal gate (HKMG) transistors, bringing the industry one step closer to the next generation of mobile devices with more computing power and vastly improved battery life.
The semiconductor industry is celebrated for overcoming seemingly insurmountable odds to continue the trend toward smaller, faster, and more energy-efficient products. Performed in partnership with IBM through GLOBALFOUNDRIES' participation in the IBM Technology Alliance, the new research is designed to enable the continued scaling of semiconductor components to the 22 nanometer node and beyond.
At the 2009 Symposium on VLSI Technology in Kyoto, Japan, GLOBALFOUNDRIES reported the first demonstration of a technique that allows the equivalent oxide thickness (EOT) in a high-k metal gate (HKMG) transistor to scale down to well beyond the level required for the 22nm node, while maintaining a combination of low leakage, low threshold voltages, and superior carrier mobility.
"HKMG is a critical component of GLOBALFOUNDRIES' technology roadmap," said Gregg Bartlett, senior vice president of technology and research and development. "This development could eventually provide customers with another tool to enhance the performance of their products, particularly in the fast-growing market for ultra-portable notebooks and smartphones with extended battery life. In conjunction with IBM and the alliance partners, we are tapping our global knowledge base to develop advanced technologies that will allow our customers to stay at the leading edge of semiconductor manufacturing."
To maintain the switching precision of a HKMG transistor, the EOT of the high-k oxide layer must be reduced. However, reducing the EOT increases the leakage current, which can contribute to an increase in the power consumption of a microchip. GLOBALFOUNDRIES and IBM have developed a new technique that overcomes this barrier, demonstrating for the first time that EOT scaling to well beyond the 22nm node can be achieved while maintaining the necessary combination of leakage, threshold voltages, and carrier mobility. The results were successfully demonstrated through fabrication of an n-MOSFET device with EOT of 0.55nm and a p-MOSFET with EOT of 0.7nm.
The semiconductor industry is celebrated for overcoming seemingly insurmountable odds to continue the trend toward smaller, faster, and more energy-efficient products. Performed in partnership with IBM through GLOBALFOUNDRIES' participation in the IBM Technology Alliance, the new research is designed to enable the continued scaling of semiconductor components to the 22 nanometer node and beyond.
At the 2009 Symposium on VLSI Technology in Kyoto, Japan, GLOBALFOUNDRIES reported the first demonstration of a technique that allows the equivalent oxide thickness (EOT) in a high-k metal gate (HKMG) transistor to scale down to well beyond the level required for the 22nm node, while maintaining a combination of low leakage, low threshold voltages, and superior carrier mobility.
"HKMG is a critical component of GLOBALFOUNDRIES' technology roadmap," said Gregg Bartlett, senior vice president of technology and research and development. "This development could eventually provide customers with another tool to enhance the performance of their products, particularly in the fast-growing market for ultra-portable notebooks and smartphones with extended battery life. In conjunction with IBM and the alliance partners, we are tapping our global knowledge base to develop advanced technologies that will allow our customers to stay at the leading edge of semiconductor manufacturing."
To maintain the switching precision of a HKMG transistor, the EOT of the high-k oxide layer must be reduced. However, reducing the EOT increases the leakage current, which can contribute to an increase in the power consumption of a microchip. GLOBALFOUNDRIES and IBM have developed a new technique that overcomes this barrier, demonstrating for the first time that EOT scaling to well beyond the 22nm node can be achieved while maintaining the necessary combination of leakage, threshold voltages, and carrier mobility. The results were successfully demonstrated through fabrication of an n-MOSFET device with EOT of 0.55nm and a p-MOSFET with EOT of 0.7nm.
18 Comments on GLOBALFOUNDRIES Details Advanced Technology Aimed at 22 nm and Beyond
Now, this probably won't be an issue, but there will be no more traditional die shrinks after 2016-2020 because we'll get to the point where gates are insulated by less than a dozen molecules. You can't control electrons in that kind of an enviornment without magnetism, and that doesn't make for controlled voltage either.
The age of nanomachines and quantum computers (if possible this soon) is only 10-15 years away! I'm excited for that :toast:
currently Intel is going for and will hit the 32nm processor segment. AMD released information a while back stating that they were going to try and skip straight to 28 nm, but said nothing else about that plan since then.
These 22 nm chips are not desktop processors and have no where near the power or complexity. This post is about mobile processors like the ARM chips in everyone's smart phones. So basically IBM is trying to enter the mobile chip market with this move and whil Global Foundaries is with AMD now, they have a none exclusive contract that allows them to work for others as well. I doubt that this will affect AMD's current plans in the slightest because this would be tech that only IBM should have access to at the moment.
"By 2014, however, the high cost of semiconductor manufacturing equipment will threaten Moore's Law, "altering the fundamental economics of the industry," according to a report released on Tuesday by iSuppli.
"The usable limit for semiconductor process technology will be reached when chip process geometries shrink to be smaller than 20 nanometers (nm), to 18nm nodes," said Len Jelinek, director and chief analyst, semiconductor manufacturing, for iSuppli. "At those nodes (levels), the industry will start getting to the point where semiconductor manufacturing tools are too expensive to depreciate with volume production, i.e., their costs will be so high, that the value of their lifetime productivity can never justify it."
here
Seriously, the technologists were right on the Discovery Channel. Maybe Technology will be so small that we will need holograms to display it.
55nm, 40nm and 28nm are called "half-nodes" and reflect the ability to reduce scale through lithographic and process improvements without changing the underlying gate technology.
Have you noted that there are GPUs made on 55nm and 40nm "half-node" points? CPU's could also be done, in theory, on these half-nodes too. Although the lifecycle of a CPU is longer than a GPU so usually there is no need to reduce CPUs to half-nodes on existing CPU architecture. It could be done however esp. in low power critical situations. The Atom CPU and ARM7/8/9 are prime candidates for half-node fabrication.
While you are correct, I don't think this is the a new tech. I think this is the same die shrinking techniques used to bring down the core size on desktops being moved over to mobile processors. While the size seems unrealistically small, think about this. The chips being built at this size have like 1/4 the number of transistors as a AMD or Intel Quad core processor at 45 nm.