43rd Symposium on VLSI Technology & Circuits to Focus on Multi-chiplet Devices and Packaging Innovations as Moore's Law Buckles
The 43rd edition of the Symposium on VLSI Technology & Circuits, held annually in Kyoto Japan, is charting the way forward for the devices of the future. Held between June 11-16, 2023, this year's symposium will see structured presentations, Q&A, and discussions on some of the biggest technological developments in the logic chip world. The lead (plenary) sessions drop a major hint on the way the wind is blowing. Leadning from the front is an address by Suraya Bhattacharya, Director, System-in-Package, A*STAR, IME, on "Multi-Chiplet Heterogeneous Integration Packaging for Semiconductor System Scaling."
Companies such as AMD and Intel read the tea-leaves, that Moore's Law is buckling, and it's no longer economically feasible to build large monolithic processors at the kind of prices they commanded a decade ago. This has caused companies to ration their allocation of the latest foundry node to only the specific components of their chip design that benefit the most from the latest node, and identify components that don't benefit as much, and disintegrate them into separate dies build on older foundry nodes, which are then connected through innovative packaging technologies.
Companies such as AMD and Intel read the tea-leaves, that Moore's Law is buckling, and it's no longer economically feasible to build large monolithic processors at the kind of prices they commanded a decade ago. This has caused companies to ration their allocation of the latest foundry node to only the specific components of their chip design that benefit the most from the latest node, and identify components that don't benefit as much, and disintegrate them into separate dies build on older foundry nodes, which are then connected through innovative packaging technologies.