ASML, the company that makes semiconductor fab machinery that powers most of today's cutting-edge foundries, has reported a fire incident in one of its plants near Berlin. The company reports that the incident occurred at night, none of its employees are injured, and that the fire is extinguished. The company says that it does not know at this point how the incident affects supplies, since it hasn't undertaken a damage-assessment. The Berlin plant of ASML manufactures components of silicon lithography equipment, including some key mechanical and optical components, such as wafer tables and clamps, reticle chucks and mirror blocks. ASML inherited this plant when it acquired Berliner Glas in 2020.

Today, ASML Holding NV (ASML) has published its 2021 third-quarter results. "Our third-quarter net sales came in at €5.2 billion with a gross margin of 51.7%, both within our guidance. Our third-quarter net bookings came in at €6.2 billion, including €2.9 billion from EUV systems. The demand continues to be high. The ongoing digital transformation and current chip shortage fuel the need to increase our capacity to meet the current and expected future demand for Memory and for all Logic nodes. ASML expects fourth-quarter net sales between €4.9 billion and €5.2 billion with a gross margin between 51% and 52%. ASML expects R&D costs of around €670 million and SG&A costs of around €195 million. For the full year, we are on track to achieving growth approaching 35%," said ASML President and Chief Executive Officer Peter Wennink.

"Moore's Law is alive and well," says ASML, in its vision document addressing investors. The company manufactures the machines that perform the actual task of silicon lithography—turning silicon discs into wafers of logic or storage chips. It highlighted the various technologies making progress, which will help its semiconductor-fabrication customers, such as TSMC and their hundreds of clients, sustain Moore's Law all the way through this decade. The company predicts SoCs with as many as 300 billion transistors by 2030. To achieve this, the company is innovating in two distinct directions—at the chip-level, to increase transistor density per chip to over 50 billion transistors; and at the system level, through packaging technology innovations, to reach that ultimate transistor count.

According to ASML's roadmap, at the turn of the decade, its technology enables 5 nm-class in production, and is at the cusp of a major breakthrough, nanosheet-FETs. which pave the way for 3 nm and 2 nm nodes, backed by EUV lithography. The journey from 2 nm to 1.5 nm will require another breakthrough, forked-nanosheets, and from 1.5 nm to 1 nm yet another breakthrough, CFET. Sub-1 nm fabrication will be possible toward the turn of this decade, thanks to 2D atomic channel technology, which is how chip-designers will be able to cram over 50 billion transistors per chip, and build MCM systems with over 300 billion transistors. The presentation predicts that besides 3D packaging, stacked silicon will also play a role, with multiple stacked logic layers, heterogenous chips with logic, storage, and I/O layers, stacked DRAM (up from single-digit layers to double-digits; and for NAND flash to grow from the current 176-layer, to nearly 500-layer by 2030.

Intel Corporation today revealed one of the most detailed process and packaging technology roadmaps the company has ever provided, showcasing a series of foundational innovations that will power products through 2025 and beyond. In addition to announcing RibbonFET, its first new transistor architecture in more than a decade, and PowerVia, an industry-first new backside power delivery method, the company highlighted its planned swift adoption of next-generation extreme ultraviolet lithography (EUV), referred to as High Numerical Aperture (High NA) EUV. Intel is positioned to receive the first High NA EUV production tool in the industry.

"Building on Intel's unquestioned leadership in advanced packaging, we are accelerating our innovation roadmap to ensure we are on a clear path to process performance leadership by 2025," Intel CEO Pat Gelsinger said during the global "Intel Accelerated" webcast. "We are leveraging our unparalleled pipeline of innovation to deliver technology advances from the transistor up to the system level. Until the periodic table is exhausted, we will be relentless in our pursuit of Moore's Law and our path to innovate with the magic of silicon."

ASML has finally finished development of EUV (Extreme Ultra Violet) pellicles to be employed in manufacturing processes that use the most energetic frequency of visible light to etch semiconductors onto wafers. Pellicles have been used for decades in the industry, and they are basically ultra-thin membranes that protect photomasks during the etching process - impeding particles from depositing in the substrate, which could lead to defects at the wafer level for every subsequent patterning that is laid on top of the impurity. Manufacturers such as TSMC have deployed EUV-powered manufacturing processes, but they have had to toil with potentially lower yields and increased costs with wafer analysis so as to reduce chances of defects appearing.

It's been a long time coming for EUV-capable pellicles, because these have different requirements compared to their traditional, non-EUV counterparts. However, once they are available on the market, it's expected that all semiconductor manufacturers with bleeding-edge manufacturing processes integrate them into their production flows. These will allow for better yields, which in turn should reduce overall pricing for the manufacturing processes. As an example, these EUV masks could be deployed on TSMC's 7 nm, 6 nm, 5 nm, and so on and so on. Other players other than ASML are also finishing their pellicle design, so the industry will have multiple options to integrate into their processes.

When the US decided to impose sanctions on all US-made technology use in foreign countries (China), the Chinese semiconductor manufacturing industry seemed at the time that it would just completely stop. Without the tools to manufacture silicon, Chinese manufacturers would need to turn to other countries to search for a possible solution. That, however, turned out impossible as the US administration has decided to stop the silicon from going into the hands of Chinese companies, by making a condition that any US-made technology can not get to China. Many of the parts for silicon manufacturing are designed in the US, so they have the power to restrict the use.

Today, in a surprising turn of events, we have information that Shanghai Micro Electronic Equipment (SMEE) has developed a deep ultraviolet (DUV) lithography scanner that is set for delivery in 2021. With a plan to deliver it in the fourth quarter of 2021, SMEE has designed this DUV scanner for the production of 28 nm node. While not being the most advanced node available to date, it is a significant start for Chinese technology independence. ASML, the producer of such scanners, used to be one of the few options there, however, it just gained a competitor. China will deliver its new silicon on a 28 nm process at the end of 2021. Pictured below, you can see how the scanner from SMEE looks like.

In the latest report by DigiTimes, it is said that TSMC has placed an order on 13 Extreme Ultra-Violet (EUV) machines from the Dutch company ASML. Thanks to the rapid increase in demand for its silicon, TSMC has developed plans for expansion across the next few years to satisfy the existing and upcoming customers. Usually, the company knows and can predict its demand for a future period. That is why TSMC is expanding its capacities with 13 additional ASML Twinscan NXE EUV scanners. These machines are set to be delivered by the course of 2021. It is unknown exactly when these machines are going to be delivered and installed at TSMC's facilities, however, it is fascinating that the demand for the company's capacities is ever-expanding. The price of single EUV machinery is as much as $175.75 million, so it is estimated that the expansion of capacity will cost TSMC a whopping $2.284,75 million. Despite the high pricing, the Return on Investment (ROI) is very high for TSMC.

SMIC is taking immense strides in bridging the gap between China's in-house silicon manufacturing capability compared to the usual Taiwanese or US-based options. Despite its ties to the Chinese government, which led for a US blacklisting of the company amidst the current China-US trade-war, SMIC has definitely achieved a benchmark with its 7 nm tape-out. This was achieved after a number of funding rounds, some of them with the power of the Chinese state behind them. While the blacklisting definitely hurt the company, they still have access to ASML's semiconductor manufacturing equipment, so while the rope may be tight, it likely isn't suffocating.

The node's first production tape-out is for an ASIC (Application-Specific Integrated Circuit) design for Innosilicon, which specializes in cryptocurrency mining, purpose-built chips. SMIC states that the new N+1 process can offer up to 20% boosted performance at the same clocks and core complexity compared to their 12 nm designs, which is subpar compared to other player's "7 nm class nodes", such as GloFo's 12 LP+, Samsung's 8LPP and TSMC's N7 non-EUV nodes (TSMC, for instance, offered a 20% performance boost between the 10 nm and 7 nm nodes). SMIC's manufacturing looks better in other metrics, though: power requirements can be reduced by 57% at the same TDP and complexity, and the transistor density can be increased by up to 2.7 times, (the "up to" depends on specific semiconductor structures). This is SMIC is only targeting - for now - low-power and low-cost devices with the N+1 nodes.

TSMC had been working super hard in the past few years and has been investing in lots of new technologies to drive the innovation forward. At TSMC's Technology Symposium held this week was, the company has presented various things like the update on its 12 nm node, as well as future plans for node development. One of the most interesting announcements made this week was TSMC's state and ownership of Extreme Ultra-Violet (EUV) machines. ASML, the maker of these EUV machines used to etch the pattern on silicon, has been the supplier of the Taiwanese company. TSMC has announced that they own an amazing 50% of all EUV machine installations.

What is more important is the capacity that the company achieves with it. It is reported that TSMC achieves 60% of all EUV wafer capacity in the world, which is a massive achievement of what TSMC can do with the equipment. The company right now has only two nodes on EUV in high-volume manufacturing, the 7 nm+ node and 5 nm node (which is going HVM in Q4), however, that is more than any of its competitors. All of the future nodes are to be manufactured using the EUV machines and the smaller nodes require it. As far as the competitors go, only Samsung is currently making EUV silicon on the 7 nm LPP node. Intel is yet to release some products on a 7 nm node of its own, which is the first EUV node from the company.

ASML Holding NV (ASML) today announced that it has completed system integration and testing of its first-generation HMI multibeam inspection (MBI) system for 5 nm nodes and beyond. The HMI eScan1000 demonstrated successful multibeam operation, simultaneously scanning nine beams on a number of test wafers. With nine beams, the eScan1000 will increase throughput up to 600% compared to single e-beam inspection tools for targeted in-line defect inspection applications.

The new MBI system includes an electron optics system capable of creating and controlling multiple primary electron beamlets and then collecting and processing the resulting secondary electron beams, limiting beam-to-beam crosstalk to less than 2% and delivering consistent imaging quality. It also features a high-speed stage to increase the system's overall throughput and a high-speed computational architecture to process the streams of data from the multiple beamlets in real time.

In a 2019 earnings call ASML, a Dutch company that is currently the world's largest semiconductor lithography supplier has been talking about the company's records and what awaits them in the future. In its 2019 earning report, ASML was forecasting the delivery of as much as 35 EUV systems in 2020. It is not a forecast per se, but rather a known fact since factories order their equipment months before they need to use it. Having previously delivered 26 EUV systems in 2019, the plan for the coming years is to boost the EUV system shipments by as much as 40% yearly. With plans to ship between 45 and 50 EUV systems in the year 2021, AMSL sees a strong revenue gain in the coming years. What is driving the demand for these machines is the use of ever-smaller semiconductor manufacturing nodes. Even at 7 nm, there is almost a need to use EUV lithography, and as you drop in size the lithography challenge becomes real, the use of EUV becomes a necessity.

During the IEDM event hosted by the IEEE organization, ASML's CEO, Martin van den Brink, took the stage to elaborate more on ASML's vision of the future of semiconductors. When talking about the future of semiconductors, Mr. Brink started talking about Intel and their vision for the future. Intel's slides were showing many things including backporting of IP to older processes and plan to go back to "tick-tock" two-year cadence to restore the previous confidence in Intel's manufacturing capabilities.

Perhaps one of the most interesting notes about the presentation is the fact that Intel is working hard to realize its plans of bringing back a two-year cadence of "tick-tock" process realization. That means that in the future, presumably after 10 nm debut problems are solved, Intel wants to do the old process and optimization tactics. A slide (shown below) titled "In Moore We Trust" is speaking a lot about Intel's future plans, showing few things in particular: Intel's upcoming 10 nm++ and 10 nm+++ nodes, and the possibility of backporting.

Semiconductor manufacturers have been historically bullish when it comes to the introduction of new manufacturing technologies. Intel, AMD (and then Globalfoundries), TSMC, all are companies who thrive in investors' confidence: they want to paint the prettiest picture they can in terms of advancements and research leadership, because that's what attracts investment, and increased share value, and thus, increased funds to actually reach those optimistic goals.

However, we've seen in recent years how mighty Intel itself has fallen prey to unforeseen complications when it comes to advancements of its manufacturing processes, which saw us go from a "tick-tock" cadence of new architecture - new manufacturing process, to the introduction of 14 nm ++ processes. And as Intel, Globalfoundries and TSMC race towards sub 7-nm manufacturing processes with 250 mm wafers and EUV usage, things aren't getting as rosy as the ultraviolet moniker would make us believe.

Silicon wafers are definitely the best kind of wafers for us tech enthusiasts, but as we all know, required financial resources for the development and production of these is among the most intensive in development costs and R&D. It's not just about the cost of employing enough (and crucially, good enough) engineers that can employ the right tools and knowledge to design the processing miracles that are etched onto wafers; there's also the cost of good, old production as well. Extreme Ultraviolet Lithography Systems that are used for the production of silicon wafers are about the size of a city bus, and typically cost more than 100 million euros ($115.3 million) each. ASML, a Dutch company that specializes in this kind of equipment, announced this year it was expecting to see a 25% revenue growth for 2017. Increased demand for these systems - and added cost of development of ever increasingly small and complex etchings in wafers - means this sector is seeing strong growth. But where there is strong growth, there is usually high demand, and high demand means higher strain on supply, which may sometimes not be able to keep up with the market's needs.

This is seemingly the case for wafer pricing; as demand for wafer production has been increasing, so to are prices. Faced with increased demand, companies are usually faced with a tough question to answer in regards to the correct course of action. Usually, it goes like this: higher demand at the same supply level means higher pricing. However, if supply isn't enough to satisfy demand, manufacturers are losing out on potential increased sales. This leads most companies to increase supply relative to demand, but always with lower projected output than demand requires, so they can bask in both increased ASP (Average Sale Price) and higher number of sales. This has been the case with DRAM memory production for some time now: and is happening with 300 mm silicon wafers as well.

TSMC has announced the location for their first 3 nm fab: it will be built in the Tainan Science Park, southern Taiwan. Rumors pegged the new 3 nm factory as possibly being built in the US, due to political reasons; however, TSMC opted to keep their production capabilities clustered in the Tainan Science Park, where they can better leverage their assets and supply chain for the production and support of the world's first 3 nm semiconductor factory. It certainly also helped the Taiwanese government's decision to pledge land, water, electricity and environmental protection support to facilitate TSMC's latest manufacturing plan. It's expected that at least part of the manufacturing machines will be provided by ASML, a Netherlands-based company which has enjoyed 25% revenue growth already just this year.

As part of the announcement, TSMC hasn't given any revised timelines for their 3 nm production, which likely means the company still expects to start 3 nm production by 2022. TSMC said its 7 nm yield is ahead of schedule, and that it expects a fast ramp in 2018 - which is interesting, considering the company has announced plans to insert several extreme ultraviolet (EUV) layers at 7 nm. TSMC has also said its 5 nm roadmap is on track for a launch in the first quarter of 2019.

Dutch company ASML may not be very known to us mortal users, but it has one of the greatest aces up its sleeve: it specializes in what are some of the most complex machines currently made by mankind. Extreme Ultraviolet Lithography Systems (EUV) are the kind of machines that make you look in wonder and amazement at man's ingenuity - ASML, which specializes in this type of systems, has a production capability for 2017 that numbers just 12 of these. That means on average, they take a whole month putting one of these together. That really goes to show the complexity inherent to these systems. And it shows: EUV machines are about the size of a city bus, and typically cost more than 100 million euros ($115.3 million) each.

The revenue growth forecast is spurred by an additional 8 EUV systems being ordered by ASML's clients, which include Intel, Samsung, and TSMC - some of the biggest players in the semiconductor business. The new orders brought the company's order backlog to 27 machines - more than double their current annual output. ASML is taking steps to to ensure an increase in production capability to keep up with the multi million-dollar demand: the company is set to expand its system production capability to 24 in 2018, before reaching an expected capacity of around 40 systems in 2019. Third-quarter revenue will be about 2.2 billion euros ($2.5 billion), the Veldhoven, Netherlands-based maker of chip-making machines predicts. The company's stock valuation has increased some 30% over the past year - the company's valuation currently stands at around €53 billion ($61 billion.)