Here are some of the first pictures of the Maxsun Intel Arc Pro B60 Dual, which as its name suggests, is a dual-GPU graphics card. This card comes with a pair of Arc Pro B60 chips, each with 24 GB of memory, for a total of 48 GB on the card. The card is a 2-slot, full-height, and over 30 cm-long beast with a lateral-blower based cooling solution. It draws power from a 600 W 12V2x6 power connector. Both GPUs on the card have their own set of display I/O—one each of DisplayPort 2.1 and HDMI 2.1b, on the rear I/O.

Internally, the Maxsun Arc Pro B60 Dual lacks a PCIe bridge chip. Since the "BMG-G21" silicon has a PCI-Express 5.0 x8 host interface, both GPUs are connected across the x16 gold finger, and rely on PCIe lane segmentation at the host level. This is precisely how M.2 NVMe riser AICs work, where they split the x16 connection among the four x4 M.2 SSDs. The primary use-case of the Arc Pro B60 Dual 48 GB is AI inferencing, and its board is designed to help you stack up to four of these cards in a workstation for 192 GB of video memory for AI models to span across. PCIe Gen 5 offers certain cache coherency features Intel introduced with CXL 1.0. Tying it all together is Intel's Project Battlematrix inference workstation platform.

Kioxia, at the 2023 China Flash Market conference (CFM), unveiled its next-generation enterprise SSD powered by 2nd Gen XL-NAND flash memory that promises up to 13.5 GB/s of sequential reads on drives with PCIe Gen 5 x4 interfaces. This puts it higher than the 12-12.5 GB/s offered by the first crop of Gen 5 SSDs, and a 118% over its current crop of Gen 4 x4 SSDs. The drive also offers up to 9.7 GB/s of sequential writes.

4K random-access performance is of a lot more importance to enterprise customers, and here, the drive is said to offer up to 3 million IOPS random reads, with up to 1.06 million IOPS sequential writes. All this comes at a slightly reduced read-latency of 27 µs, compared to 29 µs for the previous generation. Kioxia also expects PCIe Gen 5 and CXL 1.0 to be the prominent I/O interfaces for enterprise SSDs from now until the end of 2025. It's only with 2026 that we could see the emergence of PCIe Gen 6 in the enterprise space, promising a doubling in interface bandwidth.

The CXL Consortium, an industry standards body dedicated to advancing Compute Express Link (CXL) technology, today announced the release of the CXL 3.0 specification. The CXL 3.0 specification expands on previous technology generations to increase scalability and to optimize system level flows with advanced switching and fabric capabilities, efficient peer-to-peer communications, and fine-grained resource sharing across multiple compute domains.

"Modern datacenters require heterogenous and composable architectures to support compute intensive workloads for applications such as Artificial Intelligence and Machine Learning - and we continue to evolve CXL technology to meet industry requirements," said Siamak Tavallaei, president, CXL Consortium. "Developed by our dedicated technical workgroup members, the CXL 3.0 specification will enable new usage models in composable disaggregated infrastructure."

Intel has been working on CXL, short for Compute Express Link gen 1, for over four years new. This new interconnect protocol was donated to a new consortium of tech companies for release as a the CXL 1.0 standard. Its protocol layer will pave the way for PCI-Express gen 5.0 to sustain its bandwidth growth target of being twice as fast as PCIe gen 4.0. CXL 1.0 is out to compete with other established PCIe-alternative slot standards such as NVLink from NVIDIA, and InfinityFabric from AMD. It has one killer advantage, though: the CXL 1.0 is pin-compatible and backwards-compatible with PCI-Express, and uses PCIe physical-layer and electrical interface.

This reduces hardware upgrade costs for data-centers. CXL maintains memory coherency between the CPU's memory-space and memory on installed devices. The CXL Consortium, or SIG, includes data-center and cloud-computing giants, including Alibaba, Cisco, DellEMC, Facebook, Google, HPE, Huawei, Microsoft, and of course Intel. CXL will be used bot as a socketed/slotted interface for add-on cards and GPU boards, and as an embedded interface. We estimate bandwidth of CXL to be 32 Gbps per lane, or four times that of PCIe gen 3.0, keeping in line with PCIe gen 5.0 bandwidth growth estimates.