Tuesday, March 12th 2019
Intel Releases Compute Express Link (CXL) 1.0, New Interconnect Protocol that Enables PCIe gen 5.0
Intel has been working on CXL, short for Compute Express Link gen 1, for over four years new. This new interconnect protocol was donated to a new consortium of tech companies for release as a the CXL 1.0 standard. Its protocol layer will pave the way for PCI-Express gen 5.0 to sustain its bandwidth growth target of being twice as fast as PCIe gen 4.0. CXL 1.0 is out to compete with other established PCIe-alternative slot standards such as NVLink from NVIDIA, and InfinityFabric from AMD. It has one killer advantage, though: the CXL 1.0 is pin-compatible and backwards-compatible with PCI-Express, and uses PCIe physical-layer and electrical interface.
This reduces hardware upgrade costs for data-centers. CXL maintains memory coherency between the CPU's memory-space and memory on installed devices. The CXL Consortium, or SIG, includes data-center and cloud-computing giants, including Alibaba, Cisco, DellEMC, Facebook, Google, HPE, Huawei, Microsoft, and of course Intel. CXL will be used bot as a socketed/slotted interface for add-on cards and GPU boards, and as an embedded interface. We estimate bandwidth of CXL to be 32 Gbps per lane, or four times that of PCIe gen 3.0, keeping in line with PCIe gen 5.0 bandwidth growth estimates.
Source:
AnandTech
This reduces hardware upgrade costs for data-centers. CXL maintains memory coherency between the CPU's memory-space and memory on installed devices. The CXL Consortium, or SIG, includes data-center and cloud-computing giants, including Alibaba, Cisco, DellEMC, Facebook, Google, HPE, Huawei, Microsoft, and of course Intel. CXL will be used bot as a socketed/slotted interface for add-on cards and GPU boards, and as an embedded interface. We estimate bandwidth of CXL to be 32 Gbps per lane, or four times that of PCIe gen 3.0, keeping in line with PCIe gen 5.0 bandwidth growth estimates.
6 Comments on Intel Releases Compute Express Link (CXL) 1.0, New Interconnect Protocol that Enables PCIe gen 5.0
Try not to take it out of context.
This is a picture from your news article, to me it looks like a very integrate part of the on going CPU war.
AMD just upped the CPU war with going all PCIe 4.0 and now Intel already is flexing it's muskels with PCIe 5.0 saying it is better than AMD.
It is not only core count that is important in the raging CPU war, PCIe is also an extremely important part of the CPU.
Intel is simply providing a necessary solution for next get servers. As you can see, this is not an idea they came up with and try to force (like Optane or Thunderbolt 3). It was created with some of the biggest names in the server business.
Despite all the hate on forums like this one, Intel is actually a very professional company, very keen to cooperate with others.
AMD made their own interconnect, which isn't bad, but which has minimal market penetration after 2 years. They could have made it together with Dell or someone, but it was a great secret until the end.
In case you forgot, AMD has a history of this kind of secret projects. Go back 2 years, to Ryzen launch, and remind yourself how AMD treats their motherboard and cooler partners. :)Of course. And Intel-lead consortium has just given us the next big standard for servers.
This is how you fight for market dominance in the enterprise segment - not with cores and funky boxes.
Also notb, might want to do a bit of reading on what IF actually is before you jump on someone and flaunt how little you know.
CXL like IF is a protocol across pcie... they are actually quite similar in function... IF is just a bit more flexible.