Micron Technologies, in the latest earnings report, announced that they will start shipping High-Bandwidth Memory 2 (HBM2) DRAM. Used for high-performance graphics cards, server processors and all kinds of processors, HBM2 memory is wanted and relatively expensive solution, however, when Micron enters the market of its manufacturing, prices, and the market should adjust for the new player. Previously, only SK-Hynix and Samsung were manufacturing the HBM2 DRAM, however, Micron will join them and they will again form a "big-three" pact that dominates the memory market.

Up until now, Micron used to lay all hopes on its proprietary Hybrid Memory Cube (HMC) DRAM type, which didn't gain much traction from customers and it never really took off. Only a few rare products used it, as Fujitsu SPARC64 XIfx CPU used in Fujitsu PRIMEHPC FX100 supercomputer introduced in 2015. Micron announced to suspend works on HMC in 2018 and decided to devote their efforts to GDDR6 and HBM development. So, as a result, we are seeing that they will launch HBM2 DRAM products sometime this year.

Chinese chipmaker Hygon began mass-producing its first x86 processors codenamed "Dhyana" based on AMD's "Zen" micro-architecture. The processor is the fruition of a deal AMD entered with a Chinese state-owned company back in mid-2016. As part of this deal, a company called Haiguang Microelectronics Company (HMC), in which AMD has a 51 percent stake, would license the "Zen" architecture to another company called Hygon (Chengdu Haiguang Integrated Circuit Design Co.), in which AMD owns a 30 percent stake. Hygon would then design "Dhyana," and a third entity (likely TSMC or some other Chinese foundry), would contract-manufacture the chip.

Such legal gymnastics is necessary to ensure AMD makes good on the $293 million it will take from the Chinese firms to license "Zen," while not breaching the x86 architecture cross-licensing agreement it signed with Intel, the core x86 IP owner. Chinese firms are going through all this trouble to build "Dhyana" instead of simply placing a large order of EPYC processors not just because they want more control over the supply and pricing of these chips, but probably also to ensure that China can keep an eye on all the on-die software that makes the processor tick, and weed out any backdoors to foreign governments (*cough*NSA*cough*).

Avago Technologies, a leading supplier of analog interface components for wireless, wireline, and industrial applications, today announced that Micron Technology, Inc. (NASDAQ: MU) has licensed Avago's 28nm Low Power 30Gbps Serializer/Deserializer (SerDes) IP for use in Micron's next generation Hybrid Memory Cube (HMC) devices.

"Avago is an established leader in the development and delivery of high-speed SerDes cores with an offering that is very well suited for integration into our HMC product line," said Tom Eby, vice president of Micron's Compute and Networking Business Unit. "Based on its advanced performance and low power, we are confident that our customers will benefit from the presence of the Avago SerDes on both sides of the memory channel."

The Hybrid Memory Cube Consortium (HMCC), dedicated to the development and establishment of an industry-standard interface specification for the Hybrid Memory Cube (HMC) technology, today announced its continued work to build the HMC ecosystem and support for the industry adoption of this groundbreaking technology through the development of a new interface specification. Today the HMCC also released a first draft of the new specification to a growing list of consortium adopters that now numbers more than 120. The new specification supports increased data rate speeds advancing short-reach (SR) performance from 10 Gb/s, 12.5 Gb/s, and 15 Gb/s, up to 30 Gb/s. The new specification also migrates the associated channel model from SR to VSR to align with existing industry nomenclature. The ultra short-reach (USR) definition also increases performance from 10 Gb/s up to 15 Gb/s.

The HMCC, founded by leading memory providers Micron Technology (Nasdaq:MU), Samsung Electronics, and SK hynix, has begun circulating this draft specification to a broad range of adopters, with the goal of incorporating adopter members' input and targeting a completion date of May 2014 for the final version. The first-generation specification was completed and released publicly in April 2013; several developer and adopter companies, including Altera, Xilinx, and Open-Silicon, have already begun leveraging the specification to design products and solutions that incorporate HMC technology.

Micron Technology, Inc., announced today that it is shipping 2GB Hybrid Memory Cube (HMC) engineering samples. HMC represents a dramatic step forward in memory technology, and these engineering samples are the world's first HMC devices to be shared broadly with lead customers. HMC is designed for applications requiring high-bandwidth access to memory, including data packet processing, data packet buffering or storage, and computing applications such as processor accelerators. Micron expects future generations of HMC to migrate to consumer applications within three to five years.

An industry breakthrough, HMC uses advanced through-silicon vias (TSVs)-vertical conduits that electrically connect a stack of individual chips-to combine high-performance logic with Micron's state-of-the-art DRAM. Micron's HMC features a 2GB memory cube that is composed of a stack of four 4Gb DRAM die. The solution provides an unprecedented 160 GB/s of memory bandwidth while using up to 70 percent less energy per bit than existing technologies, which dramatically lowers customers' total cost of ownership (TCO).

Altera Corporation and Micron Technology, Inc. today announced they have jointly demonstrated successful interoperability between Altera Stratix V FPGAs and Micron's Hybrid Memory Cube (HMC). This technology achievement enables system designers to evaluate today the benefits of HMC with FPGAs and SoCs for next-generation communications and high-performance computing designs. The demonstration provides an early proof point that production support of HMC will be delivered with Altera's Generation 10 portfolio, in alignment with market timing, and includes both Stratix 10 and Arria 10 FPGAs and SoCs.

HMC has been recognized by industry leaders and influencers as the long-awaited answer to address the limitations imposed by conventional memory technology, and provides ultra-high system performance with significantly lower power-per-bit. HMC delivers up to 15 times the bandwidth of a DDR3 module and uses 70 percent less energy and 90 percent less space than existing technologies. HMC's abstracted memory allows designers to devote more time leveraging HMC's revolutionary features and performance and less time navigating the multitude of memory parameters required to implement basic functions. It also manages error correction, resiliency, refresh, and other parameters exacerbated by memory process variation. Micron expects to begin sampling HMC later this year with volume production ramping in 2014.

More than 100 developer and adopter members of the Hybrid Memory Cube Consortium (HMCC) today announced they've reached consensus for the global standard that will deliver a much-anticipated, disruptive memory computing solution. Developed in only 17 months, the final specification marks the turning point for designers in a wide range of segments-from networking and high-performance computing, to industrial and beyond-to begin designing Hybrid Memory Cube (HMC) technology into future products.

A major breakthrough with HMC is the long-awaited utilization of advanced technologies to combine highperformance logic with state-of-the-art DRAM. With this first HMC milestone reached so quickly, consortium members have elected to extend their collaborative effort to achieve agreement on the next generation of HMC interface standards.

Micron Technology, one of the biggest DRAM companies, has announced that it's working the JEDEC standards organization for computer memory, to standardize a new DRAM interface and die-stacking technology called three-dimensional stacking, or 3DS, which may be incorporated into the upcoming DDR4 standard. X-bit labs has a nice summary of how 3DS works:

The idea behind 3DS is to use specially designed and manufactured master-and-slave DRAM die, with only the master die interfacing with the external memory controller. 3DS technology uses optimized DRAM die, single DLL per stack, reduced active logic, single shared external I/O, improved timing, and reduced load to the external world. This combination of features can improve timing, bus speeds, and signal integrity while lowering both power consumption and system overhead for next-generation modules, according to Micron.

IBM (NYSE: IBM) and Micron Technology, Inc. announced today that Micron will begin production of a new memory device built using the first commercial CMOS manufacturing technology to employ through-silicon vias (TSVs). IBM's advanced TSV chip-making process enables Micron's Hybrid Memory Cube (HMC) to achieve speeds 15 times faster than today's technology.

Micron's Hybrid Memory Cube features a stack of individual chips connected by vertical pipelines or "vias," shown above. IBM's new 3-D manufacturing technology, used to connect the 3D micro structure, will be the foundation for commercial production of the new memory cube.

IBM will present the details of its TSV manufacturing breakthrough at the IEEE International Electron Devices Meeting on December 5 in Washington, DC.