Intel Core Ultra "Arrow Lake-S" desktop processors are expected to debut later this year, and introduce the new Lion Cove P-cores, along with Skymont E-cores to the desktop platform. Engineering samples and qualification samples with specs close to retail chips seem to already be in the hands of PC OEMs and motherboard vendors, given the volume of leaks over the past few days. Jaykihn0, one of the more influential sources of these leaks, revealed a few interesting details of the maximum boost frequencies of these chips.

The QS of a top Core Ultra 9 "Arrow Lake-S" SKU, probably the flagship model that succeeds the current Core i9-14900K, is described as having a maximum P-core boost frequency of 5.70 GHz, and an all-P-core boost frequency of 5.40 GHz. The maximum E-core boost frequency, which is also the all-E-core boost frequency, is said to be 4.60 GHz. Let's unpack this. "Arrow Lake" uses the same mix of "Lion Cove" P-cores and "Skymont" E-cores as "Lunar Lake," albeit arranged along a ringbus, and sharing an L3 cache, unlike on "Lunar Lake," where the P-cores have their own exclusive L3 cache, and the E-cores are arranged in a low-power island, with the fabric of the SoC tile connecting the two.

There is some confidence behind removing HTT (Hyper-Threading technology) for the P-cores of its upcoming processor generations. Apparently "Lunar Lake" 17 W U-segment processors offer a substantial multithreaded performance gain of almost 50% over the current-generation "Meteor Lake," enabling Intel to do away with the power- or cache overheads that come with HTT. "Lunar Lake" will be Intel's third microarchitecture powering mobile processors under the Core Ultra brand; and its U-segment SKUs meant for ultraportables will come with processor base power values of 17 W. Intel will probably revise its platform specifications for the U-segment to denote 17 W, up from the current 15 W. Bionic Squash, a reliable source with Intel leaks, suggests so. The processors will come with a configurable base power of up to 30 W.

Intel "Lunar Lake" microarchitecture has a lot in common with the upcoming "Arrow Lake." For starters, both microarchitectures use the same combination of "Lion Cove" P-core architecture, and "Skymont" E-core architecture; however "Lunar Lake" comes with changes in the core-configuration, and the use of more advanced foundry nodes for some of its tiles. "Lunar Lake," much like "Meteor Lake," comes with a design priority for mobile platforms, which is why Intel is planning to launch this shortly after "Arrow Lake," with some reports even speaking of a late-2024 debut for the U-segment.

Over the weekend, there have been a series of leaks from sources such as Golden Pig Upgrade, and High Yield YT, surrounding Intel's next-generation desktop processor, the Core Ultra 2-series "Arrow Lake-S." The lineup is likely to continue the new client processor naming scheme Intel introduced with the Core Ultra 1-series "Meteor Lake" on the mobile platform. "Arrow Lake-S" is rumored to debut the new Socket LGA1851, which retains cooler-compatibility with LGA1700. Although Intel has nucleated all I/O functions of the traditional PCH to "Meteor Lake," making it a single-chip solution on the mobile platform; and although the mobile "Arrow Lake" will continue to be single-chip; the desktop "Arrow Lake-S" will be a 2-chip solution. This is mainly because the desktop platform demands a lot more PCIe lanes, for a larger number of NVMe storage devices, or high bandwidth devices such as Thunderbolt and USB4 hubs, etc.

Another key finding in this latest series of leaks, is that unlike "Meteor Lake," the desktop "Arrow Lake-S" will do away with low-power island E-cores located in the SoC tile of the processor. All CPU cores are located in the Compute tile, which is expected to be built in the Intel 20A foundry node—the company's first node to implement GAAFETs (nanosheets), with backside power delivery; as well as an advanced 2nd generation EUV lithography. Intel's 1st Gen EUV is used on the current FinFET-based Intel 4 and Intel 3 foundry nodes.

HXL (@9550pro) has highlighted an intriguing pinned post on the Chinese Zhihu community site—where XZiar, a self described "Central Processing Unit (CPU) expert," has shared a very fuzzy/low quality screenshot of a Windows Task Manager session. The information on display indicates that a "Genuine Intel(R) 0000 1.0 GHz" processor was in use—perhaps a very early Lunar Lake (LNL) engineering sample (ES1). XZiar confirmed the pre-release nature of the onboard chip, and teased its performance prowess: "It's good to use the craftsmanship that others have stepped on. It can run 2.8 GHz with only A1 step, and it is very smooth."

The "A1" designation implies that the leaked sample is among the first LNL processor prototypes to exit manufacturing facilities—Intel previewed its "Lunar Lake-MX" SoC package to press representatives last November. XZiar's followers have pored over the screenshot and ascertained that the leaked example sports a "8-core + 8-thread, without Hyperthreading, 4P+4LPE" configuration. Others were confused by the chip's somewhat odd on-board cache designations—L1: 836 KB, L2: 14 MB and L3: 12 MB—XZiar believes that prototype's setup "is obviously not up to par," when a replier compares the spec to an N300 series processor. It is theorized that Windows Task Manager is simply not fully capable of detecting the sample's full makeup, but XZiar reckons that 12 MB of L3 cache is the correct figure.

An interesting Intel document leaked out last month—it contained detailed pre-release information that covered their upcoming 15th Gen Core Arrow Lake-S desktop CPU platform, including a possible best scenario 8+16+1 core configuration. Thorough analysis of the spec sheet revealed a revelation—the next generation Core processor family could "lack Hyper-Threading (HT) support." The rumor mill had produced similar claims in the past, but the internal technical memo confirmed that Arrow Lake's "expected eight performance cores without any threads enabled via SMT." These specifications could be subject to change, but tipster—InstLatX64—has uprooted an Arrow Lake-S engineering sample: "I spotted (CPUID C0660, 24 threads, 3 GHz, without AVX 512) among the Intel test machines."

The leaker had uncovered several pre-launch Meteor Lake SKUs last year—with 14th Gen laptop processors hitting the market recently, InstLatX64 has turned his attention to seeking out next generation parts. Yesterday's Arrow Lake-S find has chins wagging about the 24 thread count aspect (sporting two more than the fanciest Meteor Lake Core Ultra 9 processor)—this could be an actual 24 core total configuration—considering the evident lack of hyper-threading, as seen on the leaked engineering sample. Tom's Hardware reckons that the AVX-512 instruction set could be disabled via firmware or motherboard UEFI—if InstLatX64's claim of "without AVX-512" support does ring true, PC users (demanding such workloads) are best advised to turn to Ryzen 7040 and 8040 series processors, or (less likely) Team Blue's own 5th Gen Xeon "Emerald Rapids" server CPUs.

A leaked Intel documentation we reported on a few days ago covered the Arrow Lake-S platform and some implementation details. However, there was an interesting catch in the file. The leaked document indicates that the upcoming 15th-Generation Arrow Lake desktop CPUs could lack Hyper-Threading (HT) support. The technical memo lists Arrow Lake's expected eight performance cores without any threads enabled via SMT. This aligns with previous rumors of Hyper-Threading removal. Losing Hyper-Threading could significantly impact Arrow Lake's multi-threaded application performance versus its Raptor Lake predecessors. Estimates suggest HT provides a 10-15% speedup across heavily-threaded workloads by enabling logical cores. However, for gaming, disabling HT has negligible impact and can even boost FPS in some titles. So Arrow Lake may still hit Intel's rumored 30% gaming performance targets through architectural improvements alone.

However, a replacement for the traditional HT is likely to come in the form of Rentable Units. This new approach is a response to the adoption of a hybrid core architecture, which has seen an increase in applications leveraging low-power E-cores for enhanced performance and efficiency. Rentable Units are a more efficient pseudo-multi-threaded solution that splits the first thread of incoming instructions into two partitions, assigning them to different cores based on complexity. Rentable Units will use timers and counters to measure P/E core utilization and send parts of the thread to each core for processing. This inherently requires larger cache sizes, where Arrow Lake is rumored to have 3 MB of L2 cache per core. Arrow Lake is also noted to support faster DDR5-6400 memory. But between higher clocks, more E-cores, and various core architecture updates, raw throughput metrics may not change much without Hyper-Threading.

Some of you might remember Intel's Upgrade Service, aka software locked CPUs that launched back in 2010 with the Pentium G6951 that could have an extra 1 MB of cache and Hyper-Threading unlocked for a mere $50. Well, it seems like Intel is working on something similar, but for Xeon CPUs this time around, although the exact details aren't clear as yet.

Phoronix spotted a Linux patch on GitHub for something called Intel Software Defined Silicon or SDSi for short. It's clear that it's for Xeon CPUs and the GitHub page mentions that SDSi "allows the configuration of additional CPU features through a license activation process." There's very little to go by beyond this, but it's not hard to draw parallels with Intel's Upgrade Service from last decade, just this time Intel is targeting its business customers rather than consumers.

Intel today launched its newest generation Intel Xeon W-3300 processors, available today from its system integrator partners. Built for advanced workstation professionals, Intel Xeon W-3300 processors offer uncompromised performance, expanded platform capabilities, and enterprise-grade security and reliability in a single-socket solution.

Intel Xeon W-3300 processors are intelligently engineered to push the boundaries of performance, with a new processor core architecture that transforms for what expert workstation users can accomplish on a workstation.

The Intel Xeon W-3300 processors are designed for next-gen professional applications with heavily threaded, input/output-intensive workloads. Use cases stretch across artificial intelligence (AI), architecture, engineering, construction (AEC), and media and entertainment (M&E). With a new processor core architecture to transform efficiency and advanced technologies to support data integrity, Intel Xeon W-3300 processors are equipped to deliver uncompromising workstation performance.

TUM_APISAK has done of his well-regarded snoopings again, and this one could have relevant information for the democratization of threads in next-gen Intel products. Intel has been slowly (as they can) increasing the amount of cores and threads in their respective product lines across i3, i5, and i7 CPUs after AMD's Ryzen onslaught. Luckily, from two core, four-thread Core i3 of a few years ago, we now seem to be entering a new era for entry-level computing, with a new SiSoftware benchmark seemingly showing an Intel next-gen "Comet Lake" Core i3 CPU sporting 4 physical threads with Hyper Threading enabled (so, basically, the equivalent of Skylake Core i7's from just three years ago).

The benchmark submission lists what appears to be a four-core, eight-thread Core i3-10100. It sports a 3.6 GHz base clock, which likely isn't final, so take that frequency with a grain of salt. This shuffle in the low-end definitely means an upscale in Intel's more powerful lineups, with HyperThreading likely being active for all of their product stack across Comet Lake - 4C, 8T Core i3; 6C, 12T Core i5; 8C, 16T Core i7; and a likely 10C, 20T Core i9 10900K that straddles the line between consumer and HEDT platforms. Of course, remember these are still built upon the 14 nm process, give or take a few "+" symbols, so don't expect too much in terms of energy efficiency gains.

Apple has advised users that they should disable Intel's Hyper-Threading feature on the company's computers due to the recently exposed MDS vulnerabilities. Citing internal testing, Apple said that users can expect an up to 40% performance loss in such a scenario (depending on system and workload, naturally) in various benchmarks and multithreaded workloads. The performance loss is understandable - you're essentially halving the number of threads available for your CPU to process data.

Like Intel said, it becomes an issue of how much users value their performance compared to the security risks involved: a classic risk/benefit scenario, which shouldn't ever be in the equation, after all. If users buy a system with a CPU that has known performance levels, they will obviously expect those to be valid for the longevity of the product, unless otherwise stated and considering operational variances that fall within a margin of error/product obsolescence. Halving your performance because of a design flaw that resulted from an effort to achieve higher and higher IPC increases doesn't strike as a way to inspire confidence in your products.

Ouch doesn't even begin to describe how much that headline hurt. As far as speculative execution goes, it's been well covered by now, but here's a refresher. Speculative execution essentially means that your CPU tries to think ahead of time on what data may or may not be needed, and processes it before it knows it's needed. The objective is to take advantage of concurrency in the CPU design, keeping processing units that would otherwise be left idle to process and deliver results on the off-chance that they are indeed required by the system: and when they are called for, the CPU saves time by not having to process them on the fly and already having them available.

The flaws have been announced by Intel in coordination with Austrian university TU Graz, Vrije Universiteit Amsterdam, the University of Michigan, the University of Adelaide, KU Leuven in Belgium, Worcester Polytechnic Institute, Saarland University in Germany and security firms Cyberus, BitDefender, Qihoo360 and Oracle. While some of the parties involved have named the four identified flaws with names such as "ZombieLoad", "Fallout", and RIDL, or "Rogue In-Flight Data Load", Intel is using the PEGI-13 "Microarchitectural Data Sampling (MDS)" name.

Anand Srivatsa, Vice President of Intel, officially announced their all-new 9th generation of core processors in today's live stream. While the Coffee Lake refresh has certainly been no secret, a few facts were confirmed today. The Core i9-9900k will be Intel's first broad volume 5 GHz processor and is their first mainstream 8 core, 16 thread offering. In order to facilitate better overclocking results for enthusiasts, the company also confirmed that they will use solder TIM for the whole range of products, which should result in not only better overclocking potential but much lower thermals as well.

Lead developer for OpenBSD Mark Kettenis has announced that OpenBSD will no longer enable Hyper-Threading on Intel processors by default. This move is intended to mitigate security exploits from the Spectre ecosystem as well as TLB and cache timing attacks, because important processor resources are no longer shared between threads. Their suspicion is that some of the unreleased (or yet unknown) attacks can be stopped using this approach.

This move is supported by the fact that most newer motherboards no longer provide an option to disable Hyper-Threading via BIOS. OpenBSD users who still want to use Hyper-Threading can manually enable support for it using the sysctl hw.smt. The developers are also looking into expanding this feature to other CPUs from other vendors, should they be affected, too.