Intel in its Architecture Day presentation Thread Director, a hardware component present on the "Alder Lake" silicon, which makes the Hybrid architecture of the processor work flawlessly. "Alder Lake-S" is the first desktop processor with two kinds of x86 CPU cores—the larger Performance P-cores, and the smaller Efficient E-cores, which work in a setup not unlike big.LITTLE by Arm.

The x86-based "Alder Lake" processor has a much more complex ISA, and the E-cores don't have all of the instruction sets or hardware capabilities that the P-cores do. The two cores operate at very different performance/Watt bands, and are optimized for vastly different workloads. At the same time, sending a workload to the wrong kind of core could not only impact performance, but also crash, due to an ISA mismatch. Intel realized that it will take a lot more than mere OS-level awareness to solve the problem, and so innovated the Thread Director.

Armed with up to 8 "Golden Cove" high-performance CPU cores and up to 8 "Gracemont" low-power cores in a hybrid x86 processor setup, the "Alder Lake" silicon enables Intel to carve out some interesting SKUs in the mobile space, by creating numerous combinations of the big and small CPU core counts, and more importantly, by adjusting the ratio of big cores to small ones. The two core types operate at significantly different performance/Watt bands, which allows Intel to target the various TDP-defined mobile processor SKU categories with just the right big:small core ratios, as revealed by a leaked "Alder Lake" mobile SKU roadmap, leaked to the web by HXL.

Intel is looking to spread the silicon across six mobile segments defined by TDP—the 5 W tablet/handheld; the 9 W ultra-thin, the 15 W mainstream tablet/laptop, the 28 W performance tablet/laptop, the 35-45 W thin enthusiast laptop, and the 45-55 W "muscle" laptop. With Intel recently announcing the discontinuation of its 1+4 (big+small) core "Lakefield" hybrid processor, its mantle in the 5 W segment will be picked up by "Alder Lake-M5," with 1 "Golden Cove" and 4 "Gracemont" cores. There will be two product tiers segmented by iGPU execution units (EUs), one with 48 EU, and the other with 64.

Intel on Tuesday issued product-change notifications (PCNs) to announce the discontinuation of its first Hybrid processors, codenamed "Lakefield," besides 15-Watt U-segment variants of its "Ice Lake" and "Comet Lake" mobile processors. With the product discontinuation notice put out, it sets the ball rolling toward a year-long process where Intel solicits its final orders for these chips from OEMs and distributors, fulfills these orders last by 2022, and marks these parts "End of Life" (EOL).

Intel's mobile processor segment is dominated by the "Tiger Lake" microarchitecture on the 10 nm SuperFin node. Quad-core variants of the architecture cover the 15 W Y- and U-segments, while 8-core variants span the 35 W to 55 W H-segments for mainstream notebooks. Intel's next hybrid mobile processor, the "Alder Lake-P," is expected arrive in Q4-2021.

The recently leaked Windows 11 build appears to include certain optimizations for hybrid architecture processors. The developer preview provides a small improvement to Intel Lakefield processors and that boost will likely increase when Windows 11 officially launches. The Intel Lakefield processor family features a hybrid core design with 1 big core and 4 small cores, this is similar to the Apple M1 and similar hybrid designs are expected from AMD in the future. The Intel Lakefield Core i7-L16G7 CPU was tested by HotHardware and they measured performance improvements of 2% - 8% in various synthetic benchmarks including GeekBench 5, Cinebench R23, and PCMark 10. These performance improvements will benefit Intel's upcoming 12th generation Alder Lake processors and their Raptor Lake successors along with AMD's rumored Strix Point APUs.

Intel is preparing its 12th Gen Core "Alder Lake" processors to target not just desktop, but also notebook. The "Alder Lake-P" mobile processor will be Intel's second to implement a hybrid CPU core design (after "Lakefield"). Coelacanth Dream revealed the power level (PL) values of the three key variants of the "Alder Lake-P" silicon. Intel will create broadly three categories of mobile chips targeting specific notebook form-factors—15 W, 28 W, and 45 W. The "Alder Lake-U" 15 W chips are expected to have a PL1 value (interchangeable with the TDP marked on the tin), of 15 W, but its PL2 value, which enables the highest Turbo frequency, can be as high as 55 W.

The next category, the "Alder Lake-U" 28 W chips, have a PL2 value of 64 W. Lastly, the "Alder Lake-H" 45 W chip, which will go into notebooks of conventional thickness, is expected to have a PL2 value of a scorching 115 W. Unless we're mistaken, "Alder Lake-P" is a hybrid processor with up to 6 "Golden Cove" performance CPU cores, and up to 8 "Gracemont" low-power cores. The performance cores feature HyperThreading, and are AVX-512 capable. Unlike the desktop "Alder Lake-S," Intel is investing in a larger iGPU. Based on the Gen12 Xe LP graphics architecture, the iGPU of the "Alder Lake-P" could feature 96 execution units, compared to just 48 on the "Alder Lake-S."

FinalWire Ltd. today announced the immediate availability of AIDA64 Extreme 6.30 software, a streamlined diagnostic and benchmarking tool for home users; the immediate availability of AIDA64 Engineer 6.30 software, a professional diagnostic and benchmarking solution for corporate IT technicians and engineers; the immediate availability of AIDA64 Business 6.30 software, an essential network management solution for small and medium scale enterprises; and the immediate availability of AIDA64 Network Audit 6.30 software, a dedicated network audit toolset to collect and manage corporate network inventories.

The latest AIDA64 update introduces optimized benchmarks for Intel "Tiger Lake" and "Rocket Lake" processors, monitoring of sensor values on SteelSeries Apex TKL OLED displays, and supports the latest AMD and Intel CPU platforms as well as the new graphics and GPGPU computing technologies by both AMD and NVIDIA.

DOWNLOAD: AIDA64 Extreme v6.30

In a sign of AMD's answer to Intel Hybrid tech being quite far away from implementation in a product, the company filed patents to a rival/similar technology only as recently as June 30, 2020, with the patent application being dug up by Underfox. The patent calls for a multi-core processor topology with two kinds of CPU cores - a "high-feature" core (big core), and a "low-feature" one (small core).

Here's where AMD's design is different: it calls for closely integrated groups of the two kinds of cores (one big core, and one small core), called "Processor Clusters." The dedicated L1 caches of the big and small cores in each group shadow data, while an L2 cache is shared between the two cores. Several such big+small Processor Clusters sit across a die, sharing the chip's last-level cache (L3 cache). This is unlike Intel's Hybrid design, where the big and small cores are spread apart on the die, with little cache coherency (Lakefield die-shot by le Comptoir du Hardware below). The patent also details the workflow of how the processor reconciles the ISA differences between the two core types.

A Linux kernel patch contributed and signed off by Intel confirms that its upcoming Core "Alder Lake" processor will feature a hybrid core topology, much like Core Hybrid "Lakefield." The patch references "Lakefield" and "Alder Lake" under "Hybrid Core/Atom Processors." The patch possibly gives the Linux kernel awareness of the hybrid core topology, so it can schedule its work between the two types of cores on the silicon accordingly, and avoid rotating between the two core groups. Under the Android project, Linux has been aware of a similar tech from Arm since 2013.

Analogous with Arm big.LITTLE, the Intel Hybrid Core technology involves two kinds of CPU cores on a processor die, the first kind being "high performance," and the second being "low power." On "Lakefield," Intel deployed one "Sunny Cove" high performance core, and four "Tremont" low power cores. The low power cores keep the machine ticking through the vast majority of time when processing workloads requiring the high performance cores aren't present. With "Alder Lake," Intel is expected to scale up this concept, with the silicon rumored to feature eight "Golden Cove" high performance cores, and eight "Gracemont" low power ones. The chip is also expected to feature a Gen12 Xe iGPU.

A performance review of the Intel Core i5-L16G7 "Lakefield" Hybrid processor (powering a Samsung Galaxy S notebook) was recently published by Golem.de, which provides an in-depth look at Intel's ambitious new processor design that sets in motion the two new philosophies Intel will build its future processors on - packaging modularity provided by innovative new chip packaging technologies such as Foveros; and Hybrid processing, where there are two sets of CPU cores with vastly different microarchitectures and significantly different performance/Watt curves that let the processor respond to different kinds of workloads while keeping power-draw low. This concept was commercially proliferated first by Arm, with its big.LITTLE topology that took to the market around 2013. The "Lakefield" i5-L16G7 combines a high-performance "Sunny Cove" CPU core with four smaller "Tremont" cores, and Gen11 iGPU.

The Golem.de report reveals that Windows 10 thread scheduler is aware of the hybrid multi-core topology of "Lakefield," and that it is able to classify workloads at a very advanced level so the right kind of core is in use at any given time. The "Sunny Cove" core is called upon when interactive vast serial processing loads are in demand. This could even be something like launching applications, new tabs in a multi-process web-browser, or less-parallelized media encoding. The four "Tremont" cores keep the machine "cruising," handling much of the operational workload of an application, and is also better tuned to cope with highly parallelized workloads. This is similar to a hybrid automobile, where the combustion engine provides tractive effort from 0 kph, while the electric motor sustains a cruising speed.

Intel's 12th Gen Core "Alder Lake-S" desktop processors in the LGA1700 package could see the desktop debut of Intel's Hybrid Technology that it introduced with the mobile segment "Lakefield" processor. Analogous to Arm big.LITTLE, Intel Hybrid Technology is a multi-core processor topology that sees the combination of high-performance CPU cores with smaller high-efficiency cores that keep the PC ticking through the vast majority of the time/tasks when the high-performance cores aren't needed and hence power-gated. The high-performance cores are woken up only as needed. "Lakefield" combines one "Sunny Cove" high-performance core with four "Tremont" low-power cores. "Alder Lake-S" will take this concept further.

According to Intel slides leaked to the web by HXL (aka @9550pro), the 10 nm-class "Alder Lake-S" silicon will physically feature 8 "Golden Cove" high-performance cores, and 8 "Gracemont" low-power cores, along with a Gen12 iGPU that comes in three tiers - GT0 (iGPU disabled), GT1 (some execution units disabled), and GT2 (all execution units enabled). In its top trim with 125 W TDP, "Alder Lake-S" will be a "16-core" processor with 8 each of "Golden Cove" and "Gracemont" cores enabled. There will be 80 W TDP models with the same 8+8 core configuration, which are probably "locked" parts. Lastly, there the lower wrungs of the product stack will completely lack "small" cores, and be 6+0, with only high-performance cores. A recurring theme with all parts is the GT1 trim of the Gen12 iGPU.

The first homebrew processor for Macs by Apple could leverage Arm big.LITTLE technology, according to a slide from a developer-relations presentation leaked by Erdi Özüağ of Donanim Haber. Apple is referring to the setup as "asymmetric cores" in its documentation, although it essentially is big.LITTLE, a technology that's been implemented by Arm SoC vendors since 2012. It combines groups of low-power (high-efficiency) and high-performance (low-efficiency) cores in response to processing demands by software, with the high-performance cores only been engaged when needed. Intel only recently introduced its rendition of this tech, called Hybrid Processing, with its Core "Lakefield" processor, and looks to scale it up with future chips such as "Meteor Lake."

Besides a multi-core big.LITTLE CPU, the Apple SoC features dedicated AI acceleration hardware, including a neural engine and matrix-multiplication hardware (dubbed ML accelerators), a dedicated video hardware encoder and decoder, and memory controller that's optimized for UMA (unified memory) for the iGPU and system memory. Apple has already started shipping Mac Mini prototypes with an Arm-based processor to its ISVs along with a special version of MacOS "Big Sur" and a wealth of software development kit to help port their x86 Mac software over to the new machine architecture.

Performance benchmarks have started leaking for Intel-s upcoming Lakefield CPUs - low-power SoCs designed with Intel's latest technology. The Lakefield family of CPUs will make use of an Arm-similar big.LITTLE design, where this particular CPU, the Core i5-L16G7, will ship with four low-power "Tremond" cores and one large, high-performance "Sunny Cove" core for peak workloads. Built using Intel's Foveros stacking technology, these are the first chips to be built on Intel's modular platform, which should allow for pairing of I/O dies, chiplet-like CPU arrangements and memory in a 3D package. Physical distance reductions impact latency and power consumption, which should allow for an interesting design result.

Notebookcheck has tested an Intel Lakefield Core i5-L16G7 CPU that's being deployed on upcoming Samsung's Galaxy Book S, and the results are sort of a mixed bag. For one, Intel's Lakefield seems to be around 67% slower than the company's previous ultra-low-power architecture, Amber Lake. Something of this might have been caused by the fact that the Lakefield CPU didn't boost towards its advertised 3.0 GHz; it only managed to reach 2.4 GHz, which obviously hampered performance. Perhaps pre-release silicon is the culprit, or perhaps it's the galaxy Book S that's been configured with more restrictive thermal and power characteristics than the chip was actually designed to run at. The chip did manage to run the FireStrike test beating the Amber Lake-based Acer Swift 7 by 23%, though, so not all is looking bleak.

Apple on Monday formalized the beginning of its departure from Intel x86 machine architecture for its Mac computers. Apple makes up to 4 percent of Intel's annual CPU sales, according to a MarketWatch report. Apple is now scaling up its own A-series SoCs that use Arm CPU cores, up to performance levels relevant to Macs, and has implemented support for not just new and upcoming software ported to the new Arm machine architecture, but also software over form the iOS and iPadOS ecosystems on Mac, starting with its MacOS "Big Sur" operating system. We reached out to Intel for some of its first comments on the development.

In a comment to TechPowerUp, an Intel spokesperson said "Apple is a customer across several areas of our business, and we will continue to support them. Intel remains focused on delivering the most advanced PC experiences and a wide range of technology choices that redefine computing. We believe Intel-powered PCs—like those based on our forthcoming Tiger Lake mobile platform—provide global customers the best experience in the areas they value most, as well as the most open platform for developers, both today and into the future."

Today, Intel launched Intel Core processors with Intel Hybrid Technology, code-named "Lakefield." Leveraging Intel's Foveros 3D packaging technology and featuring a hybrid CPU architecture for power and performance scalability, Lakefield processors are the smallest to deliver Intel Core performance and full Windows compatibility across productivity and content creation experiences for ultra-light and innovative form factors.

"Intel Core processors with Intel Hybrid Technology are the touchstone of Intel's vision for advancing the PC industry by taking an experience-based approach to designing silicon with a unique combination of architectures and IPs. Combined with Intel's deepened co-engineering with our partners, these processors unlock the potential for innovative device categories of the future," said Chris Walker, Intel corporate vice president and general manager of Mobile Client Platforms.

Samsung Electronics today announced the availability of Galaxy Book S with Intel processor, the latest addition to its leading computing device family. To ensure consumers have access to a wide range of computing devices to best fit their lifestyle, Samsung introduces the Galaxy Book S powered by the new dynamic Intel Core processor with Intel Hybrid Technology. Galaxy Book S joins other previously announced premium mobile laptops, designed to offer a seamless and connected experience across devices. Galaxy Book S is built for the next generation of users who are looking for a computing device that provides outstanding productivity, wide-ranging connectivity, enhanced mobility and expansive continuity across devices and operating systems to help them get more done in less time.

"The way we work has shifted and it's important we have computing devices that can adapt to this new working style. Users utilize multiple devices throughout their day to accomplish tasks, and demand that those devices provide them with enough flexibility to remain on the move and available," said Woncheol Chai, SVP and Head of Product Planning Team, Mobile Communications Business, Samsung Electronics. "With our new computing devices like the Galaxy Book S, we are providing users with an exciting opportunity to be productive, efficient and connected."

One of the first Intel "Lakefield" heterogenous processor-powered devices, a Samsung Galaxy Book S model, is listed by Samsung on its Canadian online store. The Galaxy Book series typically consists of Arm-powered clamshell/convertible notebooks that use Windows 10 (Arm version). The device in question is a Galaxy Book S 13.3-inch notebook bearing model number NP767XCM-K01CA, and comes in two color trims - "Mercury Gray" and "Earthy Gold."

Under the hood is an Intel Core i5-L16G7 "Lakefield" heterogenous processor that has four "Tremont" low-power cores, and a "Sunny Cove" high-performance cores, in an arrangement rivaling Arm big.LITTLE, the first of many such chips from the company, as it taps into new technologies such as heterogenous cores and advanced Foveros chip packaging to design its future processors. The notebook offers Full HD resolution, 8 GB of RAM, 256 GB or 512 GB of solid-state NVMe storage, 802.11ax 2x2 WLAN, and a 42 Wh battery, possibly with double-digit hour battery life. All of this goes into a 6.2 mm (folded) device weighing under a kilogram.

The 11th generation Intel Core "Tiger Lake" mobile processor and pioneering "Lakefield" heterogenous x86 processor could debut around September or October, 2020, according to a leaked Lenovo internal slide posted by NotebookCheck. It also points to Intel denoting future processors' lithography with Foveros 3D Packaging as simply "3D," and not get into a nanometer number-game with AMD (which is now in 7 nm and on course to 5 nm in 2022). This makes sense as Foveros allows the combination of dies built on different silicon fabrication nodes.

"Tiger Lake" is still denoted as a 10 nm as it's a planar chip. Intel is developing it on a refined 10 nm+ silicon fabrication process, which apparently enables Intel to increase clock speeds without breaking the target power envelope. "Tiger Lake" sees the commercial debut of Intel's ambitious Xe graphics architecture as an iGPU solution. "Lakefield," on the other hand, is a 5-core processor combining four "Tremont" low power x86-64 cores with a "Sunny Cove" high-powered core, in a setup rivaling Arm big.LITTLE, enabling the next generation of mobile computing form-factors, which Intel and its partners are still figuring out under Project Athena.

Intel is preparing lots of interesting designs for the future and it is slowly shaping their vision for the next generation of computing devices. Following the big.LITTLE design principle of Arm, Intel decided to try and build its version using x86-64 cores instead of Arm ones, called Lakefield. And we already have some information about the new Alder Lake CPUs based on Lakefield design that are set to be released in the future. Thanks to a report from Chrome Unboxed, who found the patches submitted to Chromium open-source browser, used as a base for many browsers like Google Chrome and new Microsoft Edge, there is a piece of potential information that suggests Alder Lake CPUs could arrive very soon.

Rumored to feature up to 16 cores, Alder Lake CPUs could present an x86 iteration of the big.LITTLE design, where one pairs eight "big" and eight "small" cores that are activated according to increased or decreased performance requirements, thus bringing the best of both worlds - power efficiency and performance. This design would be present on Intel's 3D packaging technology called Foveros. The Alder Lake CPU support patch was added on April 27th to the Chrome OS repository, which would indicate that Intel will be pushing these CPUs out relatively quickly. The commit message titled "add support for ADL gpiochip" contained the following: "On Alderlake platform, the pinctrl (gpiochip) driver label is "INTC105x:00", hence declare it properly." The Chrome Unboxed speculates that Alder Lake could come out in mid or late 2021, depending on how fast Intel could supply OEMs with enough volume.

Intel's first client-segment processor microarchitecture built on its own 7 nm silicon fabrication process will be codenamed "Meteor Lake." The codename began surfacing in driver files and technical documents, one of which was screengrabbed and leaked to the web by Komachi Ensaka. Not much else is known about it, except that it succeeds the 10 nm++ "Alder Lake," an ambitious attempt by Intel to replicate Arm big.LITTLE heterogenous core technology on the x86 architecture, by combining a number of high-power cores with high-efficiency cores on a single piece of silicon. Intel "Lakefield," headed toward mass-production within this year, is the first such heterogenous core.

Older reports throughout 2019-20 speculate "Meteor Lake" (known at the time only by its name), could come out at a time when Intel monetizes its "Golden Cove" high-performance CPU core. It's quite likely that like "Alder Lake," it could be a heterogenous chip targeting several client form-factors, mobile and desktop. The company could leverage its 7 nm process - claimed to rival TSMC 5 nm-class in transistor density - in turning up core-counts over "Alder Lake." We'll learn more about "Meteor Lake" as we crawl toward its 2022 launch window, if it still holds up.

A leaked Intel internal slide surfaced on Chinese social networks, revealing five new products the company will build on its 10 nm silicon fabrication process. These include the "Alder Lake" heterogenous desktop processor, "Tiger Lake" mobile processor, "Ice Lake" based Xeon Scalable enterprise processors, DG1 discrete GPU, and "Snow Ridge" 5G base-station SoC. Some, if not all of these products, will implement Intel's new 10 nm+ silicon fabrication node that is expected to go live within 2020.

"Alder Lake" is a desktop processor that implements Intel's new heterogenous x86 core design that's making its debut with "Lakefield." The chip features up to 8 larger "Willow Cove" or "Golden Cove" CPU cores, and up to 8 smaller "Tremont" or "Gracemont" cores. This 8-big/8-small combo lets the chip achieve TDP targets around 80 Watts. Next up is "Tiger Lake," Intel's next-generation mobile processor family succeeding "Ice Lake." This microarchitecture implements "Willow Cove" CPU cores in a homogeneous setup, alongside Xe architecture based integrated graphics. "Ice Lake-SP" is Intel's next enterprise architecture that places mature "Sunny Cove" CPU cores in extreme core-count dies. Lastly, there's "Snow Ridge," an SoC purpose built for 5G base-stations. Image quality notwithstanding, these slides don't appear particularly new, and it's likely that COVID-19 has destabilized the roadmap. For instance, "Alder Lake," and "Ice Lake-SP" are expected to be 10 nm++ chips, a node that doesn't go live before 2021.

Intel has been experimenting with a concept of mixing various types of cores in a single package with a design called Lakefield. With this processor, you would get a package of relatively small dimensions that are 12-by-12-by-1 millimeters withing very low TDP. Thanks to the Twitter user InstLatX64 (@InstLatX64) we have some GeekBench 5 results of the new Lakefield chip. The CPU in question is the Core i5-L15G7, a 5 core CPU without HyperThreading. The 5C/5T would be a weird configuration if only Lakefield wasn't meant for such configs. There are one "big" Sunny Cove core and four "small" Tremont cores built on the 10 nm manufacturing process. This is the so-called compute die, where only the CPU cores are present. The base dies containing other stuff like I/O controllers and PHYs, memory etc. is made on a low-cost node like 22 nm, where performance isn't the primary target. The whole chip is targeting the 5-7 W TDP range.

In the GeekBench 5 result we got, the Core i5-L15G7 is a processor that has a base frequency of 1.4 GHz, while in the test it reached as high as 2.95 GHz speeds. This is presumably for the big Sunny Cove cores, as Tremont cores are supposed to be slower. The cache configuration reportedly puts 1.5 MB of L2$ and 4 MB of L3$ for the CPUs. If we take a look at performance numbers, the chip scores 725 points in single-core tests, while the multi-core result is 1566 points. We don't know what is the targeted market and what it competes with, however, if compared to some offerings from Snapdragon, like the Snapdragon 835, it offers double the single-threaded performance with a similar multi-core score. If this is meant to compete with the more powerful Snapdragon offerings like the 8cx model, comparing the two results in Intel's fail. While the two have similar single-core performance, the Snapdragon 8cx leads by as much as 76.9% in a multi-core scenario, giving this chip a heavy blow.

The fingernail-size Intel chip with Foveros technology is a first-of-its kind. With Foveros, processors are built in a totally new way: not with the various IPs spread out flat in two dimensions, but with them stacked in three dimensions. Think of a chip designed as a layer cake (a 1-millimeter-thick layer cake) versus a chip with a more-traditional pancake-like design. Intel's Foveros advanced packaging technology allows Intel to "mix and match" technology IP blocks with various memory and I/O elements - all in a small physical package for significantly reduced board size. The first product designed this way is "Lakefield," the Intel Core processor with Intel hybrid technology.

Industry analyst firm The Linley Group recently named Intel's Foveros 3D-stacking technology as "Best Technology" in its 2019 Analysts' Choice Awards. "Our awards program not only recognizes excellence in chip design and innovation, but also acknowledges the products that our analysts believe will have an impact on future designs," said Linley Gwennap, of The Linley Group.

Intel Core i5-L16G7 is the first commercial SKU that implements Intel's "Lakefield" heterogenous x86 processor architecture. This 5-core chip features one high-performance "Sunny Cove" CPU core, and four smaller "Tremont" low-power cores, with an intelligent scheduler balancing workloads between the two core types. This is essentially similar to ARM big.LITTLE. The idea being that the device idles most of the time, when lower-powered CPU cores can hold the fort; performance cores kick in only when really needed, until which time they remain power-gated. Thai PC enthusiast TUM_APISAK discovered the first public appearance of the i5-L16G7 in an unreleased Samsung device that has the Userbenchmark device ID string "SAMSUNG_NP_767XCL."

Clock speeds of the processor are listed as "1.40 GHz base, with 1.75 GHz turbo," but it's possible that the two core types have different clock-speed bands, just like the cores on big.LITTLE SoCs. Other key components of "Lakefield" include an iGPU based on the Gen11 graphics architecture, and an LPDDR4X memory controller. "Lakefield" implements Foveros packaging, in which high-density component dies based on newer silicon fabrication nodes are integrated with silicon interposers based on older fabrication processes, which facilitate microscopic high-density wiring between the dies. In case of "Lakefield," the Foveros package features a 10 nm "compute field" die sitting atop a 22 nm "base field" interposer.

The ThinkPad brand from Lenovo has always represented serious business on the move, right from its IBM origins. At CES 2020, the company unveiled what is possibly the best foldable PC design we've seen till date, the ThinkPad X1 Fold. The X1 Fold is a 13.3-inch tablet that folds perfectly along the middle to either a book-like orientation, or as a laptop, in which the top half becomes the display, and the bottom half your keyboard of whichever possible layout. If a touchscreen keyboard doesn't appeal to you, you can dock an accessory that has a physical keyboard and trackpad.

Under the hood of the X1 Fold is an Intel "Lakefield" Hybrid x86 SoC that combines high-performance and high-efficiency x86 cores and dynamically allots workload to them while power-gating on the fly (a la ARM big.LITTLE). When it comes out mid-2020 (likely a Computex 2020 launch), the ThinkPad X1 Fold will be driven by Windows 10X, a new operating system Microsoft is designing specifically for dual-screen mobile computing devices. The Flex 5G is Lenovo's first business notebook with an integrated 5G modem (in addition to Wi-Fi 6), so you can enjoy high-speed mobile Internet on the move. Lastly, we spotted the Lenovo Ducati notebook, a co-branded product of the company's MotoGP team sponsorship.

Today, at a launch event in New York City, Microsoft previewed the Surface Neo, a category-defining device co-engineered with Intel. The dual-screen device will be powered by Intel's unique processor, code-named "Lakefield," that features an industry-first architecture combining a hybrid CPU with Intel's Foveros 3D packaging technology. It offers device-makers more flexibility to innovate on design, form factor and experience.

"The innovation we've achieved with Lakefield gives our industry partners the ability to deliver on new experiences, and Microsoft's Neo is trailblazing a new category of devices. Intel is committed to pushing the boundaries of computing by delivering key technology innovations for partners across the ecosystem," said Gregory Bryant, Intel executive vice president and general manager of the Client Computing Group.