Performance benchmarks have started leaking for Intel-s upcoming Lakefield CPUs - low-power SoCs designed with Intel's latest technology. The Lakefield family of CPUs will make use of an Arm-similar big.LITTLE design, where this particular CPU, the Core i5-L16G7, will ship with four low-power "Tremond" cores and one large, high-performance "Sunny Cove" core for peak workloads. Built using Intel's Foveros stacking technology, these are the first chips to be built on Intel's modular platform, which should allow for pairing of I/O dies, chiplet-like CPU arrangements and memory in a 3D package. Physical distance reductions impact latency and power consumption, which should allow for an interesting design result.

Notebookcheck has tested an Intel Lakefield Core i5-L16G7 CPU that's being deployed on upcoming Samsung's Galaxy Book S, and the results are sort of a mixed bag. For one, Intel's Lakefield seems to be around 67% slower than the company's previous ultra-low-power architecture, Amber Lake. Something of this might have been caused by the fact that the Lakefield CPU didn't boost towards its advertised 3.0 GHz; it only managed to reach 2.4 GHz, which obviously hampered performance. Perhaps pre-release silicon is the culprit, or perhaps it's the galaxy Book S that's been configured with more restrictive thermal and power characteristics than the chip was actually designed to run at. The chip did manage to run the FireStrike test beating the Amber Lake-based Acer Swift 7 by 23%, though, so not all is looking bleak.Looking at the screenshots, it does seem that most load is being distributed to the low power Tremond cores, which is obviously the idea in such a low-power design such as this (this assumes that the high-performance Sunny Cove core is last on the Task manager). It remains to be seen if hardware scheduling is being optimal, or if there is some sort of workload shuffle between cores due to OS mismanagement of the SoC - it is a possibility, perhaps, that the OS is shuffling data between cores, thus affecting performance benefits of L1 and L2 caches too aggressively, in an attempt to keep hotspot operating temperatures in check.There is a moment in the first benchmark though where the fifth core sees a surge in workload, moving up to 100% utilization, and then declines, giving way to more work on two other cores. This looks well in line with the expected use cases for the Sunny Cove core and Intel's thoughts on designing these chips: most users only require high performance in short bursts that need to provide as much system responsiveness as possible, such as web page loading and other similar workloads.