This week, IBM and Tokyo Electron (TEL) announced an extension of their agreement for the joint research and development of advanced semiconductor technologies. The new 5-year agreement will focus on the continued advancement of technology for next-generation semiconductor nodes and architectures to power the age of generative AI. This agreement builds on a more than two-decade partnership between IBM and TEL for joint research and development. Previously, the two companies have achieved several breakthroughs, including the development of a new laser debonding process for producing 300 mm silicon chip wafers for 3D chip stacking technology.

Now, bringing together IBM's expertise in semiconductor process integration and TEL's leading-edge equipment, they will explore technology for smaller nodes and chiplet architectures to achieve the performance and energy efficiency requirements for the future of generative AI. "The work IBM and TEL have done together over the last 20 years has helped to push the semiconductor technology innovation to provide many generations of chip performance and energy efficiency to the semiconductor industry," said Mukesh Khare, GM of IBM Semiconductors and VP of Hybrid Cloud, IBM. "We are thrilled to be continuing our work together at this critical time to accelerate chip innovations that can fuel the era of generative AI."

Today, the Department of Commerce and Natcast, the operator of the National Semiconductor Technology Center (NSTC), announced the expected location for the first CHIPS for America research and development (R&D) flagship facility. The CHIPS for America Extreme Ultraviolet (EUV) Accelerator, an NSTC facility (EUV Accelerator), is expected to operate within NY CREATES' Albany NanoTech Complex in Albany, New York, supported by a proposed federal investment of an estimated $825 million. The EUV Accelerator will focus on advancing state of the art EUV technology and the R&D that relies on it.

As a key part of President Biden's Investing in America agenda, CHIPS for America is driven by the growing need to bolster the U.S. semiconductor supply chain, accelerate U.S. leading-edge R&D, and create good quality jobs around the country. This proposed facility will bring together NSTC members from across the ecosystem to accelerate semiconductor R&D and innovation by providing NSTC members access to technologies, capabilities, and critical resources.

As a part of the CHIPS act, the US government has announced that it will set up a network for advanced chip design that goes under the name of the National Semiconductor Technology Center or NSTC. The NSTC is intended to help the US pull ahead of other nations when it comes to advanced chip design, but it's also meant to help reduce the time and maybe more importantly the cost of going from a design concept to a final commercial product. A big part of this is said to be about helping startups and entrepreneurs make prototypes and pilot runs, to enable them to bring proof of concepts to the market, so they can raise funds for a full production run.

However, it doesn't stop there, as the US government also wants the NSTC to help build and sustain a suitable workforce for the semiconductor industry, suggesting that the NSTC will be involved in academia as well as the industry itself. The NSTC is backed by the Commerce Department and it's expected to involve multiple locations nationwide, although at this point in time, it's not clear if this involves new locations outside of areas where the US based semiconductor industry is located today. Even the NSTC headquarter location has as yet to be decided, but its location alongside other sites are said to be worked out over the next few months. Time will tell if the NSTC will help bring change to the US semiconductor industry, but it seems like a step in the right direction.