On February 26, 2024, AMD received new research related to an industry-wide DRAM issue documented in "ZENHAMMER: Rowhammering Attacks on AMD Zen-based Platforms" from researchers at ETH Zurich. The research demonstrates performing Rowhammer attacks on DDR4 and DDR5 memory using AMD "Zen" platforms. Given the history around Rowhammer, the researchers do not consider these rowhammering attacks to be a new issue.

Mitigation
AMD continues to assess the researchers' claim of demonstrating Rowhammer bit flips on a DDR5 device for the first time. AMD will provide an update upon completion of its assessment.

Researchers at Graz University of Technology and the Helmholtz Center for Information Security have released their paper on CacheWarp—the latest vulnerability affecting some of the prior generation AMD EPYC CPUs. Titled CVE-2023-20592, the exploit targets first-generation EPYC Naples, second-generation EPYC Rome, and third-generation EPYC Milan. CacheWarp operates by exploiting a vulnerability in AMD's Secure Encrypted Virtualization (SEV) technology, specifically targeting the SEV-ES (Encrypted State) and SEV-SNP (Secure Nested Paging) versions. The attack is a software-based fault injection technique that manipulates the cache memory of a virtual machine (VM) running under SEV. It cleverly forces modified cache lines of the guest VM to revert to their previous state. This action circumvents the integrity checks that SEV-SNP is designed to enforce, allowing the attacker to inject faults without being detected.

Unlike attacks that rely on specific guest VM vulnerabilities, CacheWarp is more versatile and dangerous because it does not depend on the characteristics of the targeted VM. It exploits the underlying architectural weaknesses of AMD SEV, making it a broad threat to systems relying on this technology for security. The CacheWarp attack can bypass robust security measures like encrypted virtualization, posing a significant risk to data confidentiality and integrity in secure computing environments. AMD has issued an update for EPYC Milan with a hot-loadable microcode patch and updated the firmware image without any expected performance degradation. And for the remaining generations, AMD states that no mitigation is available for the first or second generations of EPYC processor (Naples and Rome) since the SEV and SEV-ES features are not designed to protect guest VM memory integrity, and the SEV-SNP is not available.

AMD EPYC class of enterprise processors has gotten infected by as many as 22 different security vulnerabilities. These vulnerabilities range anywhere from medium to high severity, affecting all three generations of AMD EPYC processors. This includes AMD Naples, Rome, and Milan generations, where almost all three are concerned with the whole 22 exploits. There are a few exceptions, and you can find that on AMD's website. However, not all seems to be bad. AMD says that "During security reviews in collaboration with Google, Microsoft, and Oracle, potential vulnerabilities in the AMD Platform Security Processor (PSP), AMD System Management Unit (SMU), AMD Secure Encrypted Virtualization (SEV) and other platform components were discovered and have been mitigated in AMD EPYC AGESA PI packages."

AMD has already shipped new mitigations in the form of AGESA updates, and users should not fear if they keep their firmware up to date. If you or your organization is running on AMD EPYC processors, you should update the firmware to avoid any exploits from happening. The latest updates in question are NaplesPI-SP3_1.0.0.G, RomePI-SP3_1.0.0.C, and MilanPI-SP3_1.0.0.4 AGESA versions, which fix all of 22 security holes.

AMD invited TechPowerUp to their launch event and editor's day coverage of Zen 2 EPYC processors based on the 7 nm process. The event was a day-long affair which included product demos and tours, and capped off with an official launch presentation which we are able to share with you live as the event goes on. Zen 2 with the Ryzen 3000-series processors ushered in a lot of excitement, and for good reason too as our own reviews show, but questions remained on how the platform would scale to the other end of the market. We already knew, for example, that AMD secured many contracts based on their first-generation EPYC processors, and no doubt the IPC increase and expected increased core count would cause similar, if not higher, interest here. We also expect to know shortly about the various SKUs and pricing involved, and also if AMD wants to shed more light on the future of the Threadripper processor family. Read below, and continue past the break, for our live coverage.21:00 UTC: Lisa Su is on the stage at the Palace of Fine Arts events venue in San Francisco to present AMD's latest developments on EPYC for datacenters, using the Zen 2 microarchitecture.21:10 UTC: AMD focuses not just on delivering a single chip, but it's goal is to deliver a complete solution for the enterprise.

A set of details on AMD's upcoming Naples platform's family of EPYC CPUs has leaked on the site videocardz.com, claiming that the top product, the EPYC 7601, will feature a turbo clock of no less than 3.2 GHz (base clocks are more moderate at around 2.2 GHz for the EPYC 7601), with a core count of 32 Zen units, and 64 threads. These clocks are pretty high for a 32-core CPU, and will probably be only for a handful of cores at a time. The EPYC 7601 is also a hot chip according to this leak, in both thermals and price. It costs over $4000 USD, and has a TDP of 180 Watts (not bad at all for a 32-core part, though!)

The rest of the lineup is detailed as well, but as this is a leak that is blatantly admitting to violating an NDA, it goes without saying this could be nothing more than a fabrication. Take it with your usual dose of healthy skepticism.

For the full details of the leak (including the rest of the expected lineup), you can view the source link below.

Intel's "Xeon Scalable" lineup is designed to compete directly with AMD's Naples platform. Naples, a core-laden, high performance server platform that relies deeply on linking multiple core complexes together via AMD's own HyperTransport derived Infinity Fabric Interconnect has given intel some challenges in terms of how to structure its own high-core count family of devices. This has led to a new mesh-based interconnect technology from Intel.

Today on their Financial Analyst Day 2017, AMD has taken the lid off their "Naples" Zen implementation. The balanced Zen core in its unrestrained, server-grade level has become EPYC, with AMD CEO Lisa Su holding the silicon in her bare hands. The new EPYC platform with its I/O performance improvements allows more GPUs to be connected to a CPU than any other platform, with up to 128 PCIe lanes being expected on these server-grade chips.

With core performance back to competitiveness, AMD is preparing to take on Intel in the HEDT "high-end desktop" segment with a new line of processors that are larger than its current socket AM4 "Summit Ridge," desktop processors, but smaller in core-count than its 32-core "Naples" enterprise processors. These could include 12-core and 16-core parts, and the picture is getting clearer with an exclusive report by Turkish tech publication DonanimHaber. The biggest revelation here that the 12-core and 16-core Ryzen processors will be multi-chip modules (MCMs) of two "Summit Ridge" dies. The 12-core variant will be carved out by disabling 1 core per CCX (3+3+3+3).

Another revelation is that the 12-core and 16-core Ryzen processors will be built in a new LGA package with pin-counts in excess of 4,000 pins. Since it's an MCM of two "Summit Ridge" dies, the memory bus width and PCIe lanes will be doubled. The chip will feature a quad-channel DDR4 memory interface, and will have a total of 58 PCI-Express gen 3.0 lanes (only one of the two dies will put out the PCI-Express 3.0 x4 A-Link chipset bus). The increase in core count isn't coming with a decrease in clock speeds. The 12-core variant will hence likely have its TDP rated at 140W, and the 16-core variant at 180W. AMD is expected to unveil these chips at the 2017 Computex expo in Taipei, this June, with product launches following shortly after.

Some rumors and whispers have been making the rounds lately, regarding a HEDT platform incoming from AMD. This platform (built upon a new X399 chipset planned exclusively for it) would use a cut-down version of the Naples-based server SP3 socket called SP3r2. SP3r2 and the new chip will reportedly offer quad channel memory support, pitting them directly in competition with Intel's HEDT lineup in terms of memory bandwidth.

Reportedly, engineering samples of the 180W 16-core Ryzen currently run at 3.1 GHz Base, 3.6 GHz Boost clocks, which leads towards performance in the level of two Ryzen 7 1700 chips. If the rumors are true and such a platform is in development, then we will surely hear of some more chips designed for it. Going through the trouble of creating a new chipset and platform for a single CPU model doesn't seem likely. Perhaps some 12-core and 20-core chips are lurking just below the surface?

At the 2017 Open Compute Project U.S. Summit, AMD announced their collaboration with Microsoft to incorporate the cloud delivery features of AMD's next-generation "Naples" processor with Microsoft's Project Olympus -- Microsoft's next-generation hyperscale cloud hardware design and a new model for open source hardware development with the OCP community.

Through Microsoft's contribution of the Project Olympus design much earlier in the cycle than many OCP projects, AMD was able to engage early on in the design process and foster a deep collaboration around the strategic integration of AMD's upcoming "Naples" processor. The performance, scalability and efficiency found at the core of Project Olympus and AMD's "Naples" processor means the updated cloud hardware design can adapt to meet the application demands of global datacenter customers.

AMD today unveiled the "Naples" enterprise processor, and it is big. The chip could mark AMD's return to competitive enterprise CPUs after years. The first "Naples" based part has some staggering specifications - 32 CPU cores spread across eight CCX units, SMT enabling 64 threads, an octa-channel (yes, eight channels) DDR4 integrated memory controller, an industry-leading 64-lane PCI-Express gen 3.0 root complex, and AMD's new Infinity Fabric interconnect, which lets it talk to the neighboring CPU, in a 2P system. The IMC supports up to 2 TB of memory.

AMD will competitively price "Naples" against Intel's Xeon E5-2600 series 2P chips, offering more cores, wider memory interfaces, more memory support, and more PCIe lanes. AMD will tap into the good energy-efficiency of its "Zen" architecture to clock these chips competitively higher than Intel chips, to churn out more overall performance. AMD is scheduled to launch the first processors based on the "Naples" silicon, within Q2-2017.