Flow Computing, the pioneer in licensing on-die, ultra-high-performance parallel computing solutions to CPU vendors of all architectures - today announced it has successfully achieved a critical milestone in Flow's development roadmap towards commercializing its parallel processing ecosystem. Capable of increasing any CPU architecture by up to 100X, the company has been actively developing a compiler that enables source code to take advantage of its acclaimed Parallel Processing Unit (PPU) architecture - that compiler today entered Alpha testing.

Through the first target compilations, it has been determined that simple parallel workloads consist of a massive amount of loops in RISC-V CPU models without PPU assistance. Whereas in RISC-V CPU models incorporating the PPU, the amount of these loops is significantly reduced by recompiling the existing code, demonstrable proof that it is indeed possible to achieve a significant performance boost with a PPU-enhanced CPU design at up to 100X performance.

Baya Systems, a leader in system IP technology that empowers the acceleration of intelligent compute, and Semidynamics, a provider of fully customizable high-bandwidth and high-performance RISC-V processor IP, today announced a collaboration to boost innovation in development of hyper-efficient, next-generation platforms for artificial intelligence (AI), machine learning (ML) and high-performance computing (HPC) applications.

The collaboration integrates Semidynamics' family of 64-bit RISC-V processor IP cores, known for their exceptional memory bandwidth and configurability, with Baya Systems' innovative WeaveIP Network on Chip (NoC) system IP. WeaveIP is engineered for ultra-efficient, high-bandwidth, and low-latency data transport, crucial for the demands of modern workloads. Complementing this is Baya Systems' software-driven WeaverPro platform, which enables rapid system-level optimization, ensuring that key performance indicators (KPIs) are met based on real-world workloads while providing unparalleled design flexibility for future advancements.

The CHERI Alliance CIC (Community Interest Company) today announced its official launch and the expansion of its membership, welcoming Chevin Technology (UK), Critical Technologies (USA), the Defence Science and Technology Laboratory (DSTL, UK), Google (USA), Light Momentum Technology Corporation (Taiwan), National Cyber Security Centre (NCSC, a part of GCHQ, UK), Parvat Infotech (India), SRI International (USA), TechWorks (UK), Trusted Computer Center of Excellence (USA), the University of Birmingham (UK), and the University of Glasgow (UK) as founding members.

Founded to unite hardware security leaders and system developers, the CHERI Alliance aims to establish CHERI (Capability Hardware Enhanced RISC Instructions) as the new standard for memory safety and scalable software compartmentalization.

In a notable step forward for the RISC-V architecture, the Box86 and Box64 emulator developers have successfully run The Witcher 3 on a RISC-V processor. While performance is far from optimal, even on a Milk-V Pioneer with a 64-core processor and an AMD Radeon RX 5500 XT graphics card, the achievement is remarkable.

RISC-V, a free and open-source instruction set architecture, is still in its early stages compared to established platforms like ARM and x86/x64. Despite this, the Box86/Box64 team, known for creating environments to run Windows programs on Linux, has demonstrated that AAA gaming is possible on RISC-V hardware. To accomplish this feat, the developers utilized Box64 with Wine and DXVK to emulate the necessary instructions.

Akeana, the company committed to driving dramatic change in semiconductor IP innovation and performance, has announced its official company launch approximately three years after its foundation, having raised over $100 million in capital, with support from A-list investors including Kleiner Perkins, Mayfield, and Fidelity. Today's launch marks the formal availability of the company's expansive line of IP solutions that are uniquely customizable for any workload or application.

Formed by the same team that designed Marvell's ThunderX2 server chips, Akeana offers a variety of IP solutions, including microcontrollers, Android clusters, AI vector cores and subsystems, and compute clusters for networking and data centers. Akeana moves the industry beyond the status quo of legacy vendors and architectures, like Arm, with equitable licensing options and processors that fill and exceed current performance gaps.

Industry leader AAEON has expanded its RISC computing product portfolio with the release of the SRG-IMX8PL and PICO-IMX8PL, a Mini PC and 2.5" PICO-ITX board, respectively. Both products are powered by the NXP i.MX 8M Plus platform, featuring a quad-core Arm Cortex -A53 processor with a Neural Processing Unit (NPU) operating at up to 2.3 TOPS.

Built to provide cost-efficient IoT Gateway solutions in rugged environments, the SRG-IMX8PL and PICO-IMX8PL both offer wide temperature ranges of -40°C to 80°C with the use of a fanless heatsink, a 9 V to 36 V power input range. The SRG-IMX8PL Mini PC also features enhanced shock, drop, and vibration resistance. Dual LAN ports with IEEE 1588 and TSN capabilities, alongside Wi-Fi and 4G module support via M.2 2230 E-Key and full-size mini card, provide each device with broad connectivity options for industrial IoT use. Additionally, both the PICO-IMX8PL and SRG-IMX8PL support a wide range of operating systems, including Debian 11, Android 13, Windows 10 IoT, and Yocto, as well as data communication protocols such as Modbus, MQTT, and OPC Unified Architecture (OPC UA).

While we are all used to having a system with a CPU, GPU, and, recently, NPU—X-Silicon Inc. (XSi), a startup founded by former Silicon Valley veterans—has unveiled an interesting RISC-V processor that can simultaneously handle CPU, GPU, and NPU workloads in a chip. This innovative chip architecture, which will be open-source, aims to provide a flexible and efficient solution for a wide range of applications, including artificial intelligence, virtual reality, automotive systems, and IoT devices. The new microprocessor combines a RISC-V CPU core with vector capabilities and GPU acceleration into a single chip, creating a versatile all-in-one processor. By integrating the functionality of a CPU and GPU into a single core, X-Silicon's design offers several advantages over traditional architectures. The chip utilizes the open-source RISC-V instruction set architecture (ISA) for both CPU and GPU operations, running a single instruction stream. This approach promises lower memory footprint execution and improved efficiency, as there is no need to copy data between separate CPU and GPU memory spaces.

Called the C-GPU architecture, X-Silicon uses RISC-V Vector Core, which has 16 32-bit FPUs and a Scaler ALU for processing regular integers as well as floating point instructions. A unified instruction decoder feeds the cores, which are connected to a thread scheduler, texture unit, rasterizer, clipping engine, neural engine, and pixel processors. All is fed into a frame buffer, which feeds the video engine for video output. The setup of the cores allows the users to program each core individually for HPC, AI, video, or graphics workloads. Without software, there is no usable chip, which prompts X-Silicon to work on OpenGL ES, Vulkan, Mesa, and OpenCL APIs. Additionally, the company plans to release a hardware abstraction layer (HAL) for direct chip programming. According to Jon Peddie Research (JPR), the industry has been seeking an open-standard GPU that is flexible and scalable enough to support various markets. X-Silicon's CPU/GPU hybrid chip aims to address this need by providing manufacturers with a single, open-chip design that can handle any desired workload. The XSi gave no timeline, but it has plans to distribute the IP to OEMs and hyperscalers, so the first silicon is still away.

Chinese e-commerce and cloud giant Alibaba announced its plans to launch a server-grade RISC-V processor later this year, and it showcased a RISC-V-powered laptop running an open-source operating system. The announcements were made by Alibaba's research division, the Damo Academy, at the recent Xuantie RISC-V Ecological Conference in Shenzhen. The upcoming server-class processor called the Xuantie C930, is expected to be launched by the end of 2024. While specific details about the chip have not been disclosed, it is anticipated to cater to AI and server workloads. This development is part of Alibaba's ongoing efforts to expand its RISC-V portfolio and reduce reliance on foreign chip technologies amidst US export restrictions. To complement the C930, Alibaba is also preparing a Xuantie 907 matrix processing unit for AI, which could be an IP block inside an SoC like the C930 or an SoC of its own.

In addition to the C930, Alibaba showcased the RuyiBOOK, a laptop powered by the company's existing T-Head C910 processor. The C910, previously designed for edge servers, AI, and telecommunications applications, has been adapted for use in laptops. Strangely, the RuyiBOOK laptop runs on the openEuler operating system, an open-source version of Huawei's EulerOS, which is based on Red Hat Linux. The laptop also features Alibaba's collaboration suite, Ding Talk, and the open-source office software Libre Office, demonstrating its potential to cater to the needs of Chinese knowledge workers and consumers without relying on foreign software. Zhang Jianfeng, president of the Damo Academy, emphasized the increasing demand for new computing power and the potential for RISC-V to enter a period of "application explosion." Alibaba plans to continue investing in RISC-V research and development and fostering collaboration within the industry to promote innovation and growth in the RISC-V ecosystem, lessening reliance on US-sourced technology.

Renesas Electronics Corporation, a premier supplier of advanced semiconductor solutions, announced today that it has designed and tested a 32-bit CPU core based on the open-standard RISC-V instruction set architecture (ISA). Renesas is among the first in the industry to independently develop a CPU core for the 32-bit general-purpose RISC-V market, providing an open and flexible platform for IoT, consumer electronics, healthcare and industrial systems. The new RISC-V CPU core will complement Renesas' existing IP portfolio of 32-bit microcontrollers (MCUs), including the proprietary RX Family and the RA Family based on the Arm Cortex -M architecture.

RISC-V is an open ISA which is quickly gaining popularity in the semiconductor industry, due to its flexibility, scalability, power efficiency and open ecosystem. While many MCU providers have recently created joint investment alliances to accelerate their development of RISC-V products, Renesas has already developed a new RISC-V core on its own. This versatile CPU can serve as a main application controller, a complementary secondary core in SoCs, on-chip subsystems, or even in deeply embedded ASSPs. This positions Renesas as a leader in the emerging RISC-V market, following previous introductions of its 32-bit voice-control and motor-control ASSP devices, as well as the RZ/Five 64-bit general purpose microprocessors (MPUs), which were built on CPU cores developed by Andes Technology Corp.

Qualcomm Technologies, Inc. announced today that they are building on their long-standing collaboration with Google by bringing a RISC-V based wearables solution for use with Wear OS by Google. This expanded framework will help pave the way for more products within the ecosystem to take advantage of custom CPUs that are low power and high performance. Leading up to this, the companies will continue to invest in Snapdragon Wear platforms as the leading smartwatch silicon provider for the Wear OS ecosystem.

"Qualcomm Technologies have been a pillar of the Wear OS ecosystem, providing high performance, low power systems for many of our OEM partners," said Bjorn Kilburn, GM of Wear OS by Google. "We are excited to extend our work with Qualcomm Technologies and bring a RISC-V wearable solution to market."
"We are excited to leverage RISC-V and expand our Snapdragon Wear platform as a leading silicon provider for Wear OS. Our Snapdragon Wear platform innovations will help the Wear OS ecosystem rapidly evolve and streamline new device launches globally," said Dino Bekis, vice president and general manager, Wearables and Mixed Signal Solutions, Qualcomm Technologies, Inc.

Shenzhen based Milk-V has been busy announcing some very high performance RISC-V based platforms, and has now added another to a rapidly growing list. The Milk-V Mars is a new hobbiest grade RISC-V SBC that intentionally mimics the footprint and layout of the Raspberry Pi 3 Model B, so much so that existing cases and accessories will fit. The credit-card sized Mars packs a very competent array of features, starting with the StarFive JH7110 SoC. The JH7110 contains four 64-bit SiFive U74 RISC-V cores clocked as high as 1.5 GHz as well as an integrated Imagination Technologies IMG BXE-2-32 graphics engine with support for Vulkan 1.3, OpenGL ES 3.x, OpenCL 3.0, and Android NN HAL. This SoC should be the perfect choice for an SBC in this form factor, as it has proven to be on the similarly sized PINE64 Star64 as well as StarFive's VisionFive 2. Surrounding the SoC is a single LPDDR4 module, configurable at purchase up to 8 GB, the traditional 40-pin GPIO header row, a M.2 E-Key for WiFi/BT expansion, a MIPI display serial interface with 4K30 output and H.264/H.265 4K60 decoding, MIPI camera serial interface, HDMI, a USB-C for 5 V power input, a 3.5 mm audio jack, and finally the rear I/O block which consists of three USB 3.0 Type-A, a single USB 2.0 Type-A, and the RJ-45 for Gigabit Ethernet as well as PoE. Storage is expandable with both eMMC and microSD cards. The last tiny header is for powering a fan, which many R Pi cases opt to include, but is not included with the Mars. Availability of the Milk-V Mars is listed as "Coming Soon" and prices have not yet been announced. However to compete with the other options on the market we hope, and expect, that it does not exceed $75 USD. Unlike the Milk-V Pioneer there hasn't been any word on whether the Mars will be as open-source friendly, but it would behoove them to consider the option for this type of hobbyist oriented device.

Chinese RISC-V developers Milk-V Technology and SOPHGO recently announced their collaborative open source Milk-V Pioneer developer motherboard and workstation based on the SOPHON SG2042 RISC-V server SoC. The SOPHON SG2042 is a 64-core, 2 GHz SoC based on T-Head Semiconductor's XuanTie C920 64-bit processor design which features clusters of one to four cores, each a 12-stage out-of-order multiple issue superscalar pipeline, and a 128-bit vector engine based on the preliminary RISC-V V Extension version 0.7.1. The SG2042 packs in 64+64 KB (I+D) L1 cache per core, 1 MB of L2 cache per core cluster, 64 MB of L3 system cache, a quad-channel DDR4 controller, and 32 lanes of PCI-E Gen 4. The SG2042 contains no integrated graphics solution.

The Milk-V Pioneer incorporates this highly threaded RISC-V SoC with a modular and expandable standard mATX motherboard featuring four DIMM slots with support for up to 128 GB of DDR4, three full-length PCI-E slots wired for Gen 4 x8, two M.2 M-Key PCI-E Gen 3 x4, one M.2 E-Key for PCI-E 3.0 x1 and USB 2.0, eight USB 3.2 10 Gbps ports, five SATA 6 Gbps ports, and a pair of 2.5G Ethernet ports. The bulk of this I/O runs off an ASMedia ASM 2824 PCI-E switch, however the PCI-E Gen 4 ports run directly off the SG2024 SoC. Milk-V Pioneer is also being offered as a prebuilt small form factor workstation which puts the board into a small portable chassis called the Pioneer Box. The Pioneer Box includes 64 GB of DDR4-3200, 1 TB M.2 SSD, an Intel X520-T2 10G network card, an AMD Radeon R5 230 graphics card for display, and a 350 W power supply.

A 64-bit Dec Alpha C compiler was found by Virtually Fun's neozeed earlier this year - the software archeologist has been searching for various test builds of Microsoft Windows NT, including an "AXP64/ALPHA64 port," deemed extra special due to it being the first 64-bit version of Windows 2000 Professional. The small discovery of this obscure compiler was celebrated, but its functionality is ultimately not all that useful - neozeed notes that the items have been sitting within 1999 vintage Windows Platform SDKs: "It turns out that the AXP64 compiler set has been hiding in plain sight for DECADES. I know that it's so unlikely that we'd ever see any public release of a 64-bit version of Windows for the Alpha, but oddly enough the compiler, headers and libraries are all there. YES. You can make full executes for AXP64/Alpha64. Of course with no OS, so it's not like you can run them."

He continues: "Sadly as of today, there is no way to test. There is one surviving machine with Windows 2003 AXP64, outlined in an article by Raymond Chen. It's a great read about how Alpha64 NT port came to be. The machine is still sitting in Microsoft Archives. Hopefully one day someone can dig it out." The story could have ended there, but a follow up post appeared on Virtually Fun earlier this week - courtesy of guest contributor Antoni Sawicki (aka tenox) who has also experimented with the cross-compiler. He provided a little bit more historical context before making an interesting announcement: "The Win64 project for AXP64 and IA64 was code named "Sundown." Sadly, 64-bit Alpha AXP Windows was never released outside of Redmond."