Rambus Inc., a premier chip and silicon IP provider making data faster and safer, today announced the availability of complete client chipsets for next-generation AI PC memory modules, featuring two new Power Management ICs (PMICs) for client computing. PMICs are critical to efficiently power memory modules providing breakthrough levels of performance for advanced computing applications. The two new Rambus industry-leading PMICs are the PMIC5200, for LPDDR5 CAMM2 (LPCAMM2) memory modules and the PMIC5120, which supports DDR5 CSODIMMs and CUDIMMs.

These PMICs, alongside the Client Clock Driver (CKD) and Serial Presence Detect Hub (SPD Hub), comprise a complete chipset offering to enable memory modules for AI PC notebooks, desktops and workstations. Further, with the addition of these new PMICs, Rambus now offers complete memory interface chipsets for all JEDEC standard DDR5 and LPDDR5 memory modules for both servers and clients.

Rambus Inc., a premier chip and silicon IP provider making data faster and safer, today unveiled industry-first, complete memory interface chipsets for Gen 5 DDR5 RDIMMs and next-generation DDR5 Multiplexed Rank Dual Inline Memory Modules (MRDIMMs). These innovative new products for RDIMMs and MRDIMMs will seamlessly extend DDR5 performance with unparalleled bandwidth and memory capacity for compute-intensive data center and AI workloads.

"The voracious memory demands of AI and HPC require the relentless pursuit of higher performance through continued innovation and technology leadership," said Sean Fan, chief operating officer at Rambus. "With our 30-plus years of renowned high-speed signal integrity and memory system expertise, the Rambus Gen5 RCD, and next-generation MRCD, MDB, and PMIC will be critical enabling chips in future-generation servers leveraging DDR5 RDIMM 8000 and MRDIMM 12800."

Rambus Inc., a premier chip and silicon IP provider making data faster and safer, today announced the industry's first HBM4 Memory Controller IP, extending its market leadership in HBM IP with broad ecosystem support. This new solution supports the advanced feature set of HBM4 devices, and will enable designers to address the demanding memory bandwidth requirements of next-generation AI accelerators and graphics processing units (GPUs).

"With Large Language Models (LLMs) now exceeding a trillion parameters and continuing to grow, overcoming bottlenecks in memory bandwidth and capacity is mission-critical to meeting the real-time performance requirements of AI training and inference," said Neeraj Paliwal, SVP and general manager of Silicon IP, at Rambus. "As the leading silicon IP provider for AI 2.0, we are bringing the industry's first HBM4 Controller IP solution to the market to help our customers unlock breakthrough performance in their state-of-the-art processors and accelerators."

Rambus Inc., a premier chip and silicon IP provider making data faster and safer, today announced the availability of its DDR5 Client Clock Driver (CKD) for next-generation, high-performance desktops and notebooks. The Rambus DDR5 CKD and SPD Hub are part of a new client memory interface chip product offering that brings server technology advancements to the client market. Leveraging over 30 years of memory system expertise, the Rambus DDR5 CKD enables new client DIMMs (CSODIMMs and CUDIMMs) to operate at state-of-the-art data rates of up to 7200 Megatransfers per second (MT/s), and deliver breakthrough performance in next-generation PCs.

"As advanced technologies first developed for the data center proliferate to the client space, increasingly powerful PCs will take gaming, content creation and AI to new levels," said Rami Sethi, SVP and general manager of Memory Interface Chips at Rambus. "This new DDR5 Client Clock Driver is the latest addition to our growing line up of chip solutions that enable breakthrough memory performance across the computing landscape, and bring more value to our customers."

Rambus Inc. (NASDAQ: RMBS), a premier chip and silicon IP provider making data faster and safer, today announced the availability of its new family of state-of-the-art DDR5 server Power Management ICs (PMICs), including an industry-leading extreme current device for high-performance applications. With this new family of server PMICs, Rambus offers module manufacturers a complete DDR5 RDIMM memory interface chipset supporting a broad range of data center use cases.

"Advanced data center workloads like generative AI require the highest bandwidth and capacity server RDIMMs tailored to meet ever-increasing memory needs of a growing data pipeline," said Sean Fan, chief operating officer at Rambus. "With the addition of this new family of server PMICs, we expand our foundational technology and offer customers a comprehensive memory interface chipset that supports multiple DDR5 server platform generations."

Rambus Inc., a premier chip and silicon IP provider making data faster and safer, today announced the availability of its state-of-the-art Gen 4 DDR5 Registering Clock Driver (RCD) which began sampling to the major DDR5 memory module (RDIMM) manufacturers in the fourth quarter of 2023. The Rambus Gen 4 RCD boosts the data rate to 7200 MT/s, setting a new benchmark for performance and enabling a 50% increase in memory bandwidth over today's 4800 MT/s DDR5 module solutions. It supports the rapid pace of server main memory performance improvements to meet the demands of generative AI and other advanced data center workloads.

"With memory being an essential enabler of server performance, the need for greater memory bandwidth continues its meteoric rise driven by demanding workloads like generative AI," said Sean Fan, chief operating officer at Rambus. "The Rambus Gen 4 DDR5 RCD is the latest demonstration of our commitment to providing leadership products ahead of the market need to support our customers' current and planned server platforms."

Rambus Inc., a premier chip and silicon IP provider making data faster and safer, today announced that the Rambus HBM3 Memory Controller IP now delivers up to 9.6 Gigabits per second (Gbps) performance supporting the continued evolution of the HBM3 standard. With a 50% increase over the HBM3 Gen 1 data rate of 6.4 Gbps, the Rambus HBM3 Memory Controller can enable a total memory throughput of over 1.2 Terabytes per second (TB/s) for training of recommender systems, generative AI and other demanding data center workloads.

"HBM3 is the memory of choice for AI/ML training, with large language models requiring the constant advancement of high-performance memory technologies," said Neeraj Paliwal, general manager of Silicon IP at Rambus. "Thanks to Rambus innovation and engineering excellence, we're delivering the industry's leading-edge performance of 9.6 Gbps in our HBM3 Memory Controller IP."

Cadence Design Systems, Inc. and Rambus Inc., a premier chip and silicon IP provider making data faster and safer, today announced that they have entered into a definitive agreement for Cadence to acquire the Rambus SerDes and memory interface PHY IP business. Rambus will retain its digital IP business, including memory and interface controllers and security IP. The expected technology asset purchase also brings Cadence proven and experienced PHY engineering teams in the United States, India and Canada, further expanding Cadence's domain-rich talent base.

"Memory and SerDes IP design and integration continues to be integral to the design of AI, data center and hyperscale applications, CPU architectures and networking devices, and the addition of the Rambus IP and seasoned team further accelerates Cadence's Intelligent System Design strategy, which drives design excellence," said Boyd Phelps, senior vice president and general manager of the IP Group at Cadence. "The acquisition of the Rambus PHY IP broadens Cadence's well-established enterprise IP portfolio and expands its reach across geographies and vertical markets, such as the aerospace and defense market, providing complete subsystem solutions that meet the demands of our worldwide customers."

Join us for the PCI-SIG Developers Conference in Santa Clara, CA and see demos of the latest Rambus PCI Express (PCIe ) 6.0 IP solutions, including 64 Gigatransfers per second (GT/s) PCIe 6.0 PHY and Controller IP. With leading PPA, these 64 GT/s products achieve high performance, low power and area-efficient footprint for compute-intensive workloads including data center, AI/ML and HPC applications.

The Rambus PCIe 6.0 Interface Subsystem comprising PHY and Controller has been fully optimized to meet the needs of advanced heterogenous computing architectures. The PCIe Controller features an Integrity and Data Encryption (IDE) engine dedicated to protecting the PCIe links and the valuable data transferred over them. The PCIe 6.0 PHY features state-of-the-art SI/PI performance to provide best-in-class design margin for first-time-right implementations.

Rambus Inc., a premier chip and silicon IP provider making data faster and safer, today announced a new product milestone for GDDR6 memory interface performance. The Rambus GDDR6 PHY delivers a market-leading data rate of up to 24 Gigabits per second (Gb/s), providing 96 Gigabytes per second (GB/s) of bandwidth per GDDR6 memory device. As part of a system-level solution, the Rambus GDDR6 offering enables cost-efficient, high-bandwidth memory performance for AI/ML, graphics and networking applications.

"With the new level of performance achieved by our GDDR6 PHY, designers can deliver the bandwidth needed by the most demanding workloads," said Sean Fan, chief operating officer at Rambus. "As with our industry-leading HBM3 memory interface, this latest achievement demonstrates our continued commitment to advancing state-of-the-art memory performance to meet the needs of advanced computing applications such as generative AI."

Rambus Inc., a premier chip and silicon IP provider making data faster and safer, today announced it has extended its comprehensive patent license agreement with SK hynix, a world leader in advanced semiconductor technology, for an additional ten years. Effective July 1, 2024, the extension maintains similar financial terms and provides SK hynix with broad access to the full Rambus patent portfolio through mid 2034. Other terms and details are confidential.

"SK hynix is a longstanding partner and customer, and we are very pleased to extend our strong relationship well ahead of the agreement's expiration date," said Luc Seraphin, president and chief executive officer of Rambus. "Both Rambus and SK hynix are committed to advancing the industry with world-class products and technology, and this extension is a testament to the ongoing value of our intellectual property and our continued product collaborations together."

Rambus Inc., a premier chip and silicon IP provider making data faster and safer, today announced the availability of its new 6400 MT/s DDR5 Registering Clock Driver (RCD) and sampling to the major DDR5 memory module (RDIMM) manufacturers. With a 33% increase in data rate and bandwidth over Gen 1 4800 MT/s solutions, the Rambus Gen 3 6400 MT/s DDR5 RCD enables a new level of main memory performance for data center servers. Delivering industry-leading latency and power, it offers optimized timing parameters for improved RDIMM margins.

"Data center workloads have an insatiable thirst for greater memory bandwidth and capacity, and our mission is to advance the performance of server memory solutions that meet this need for each new server platform generation," said Sean Fan, chief operating officer at Rambus. "We were first in the industry to 5600 MT/s, and now we have raised the bar with our Gen 3 DDR5 RCD capable of 6400 MT/s to support a new generation of RDIMMs for server main memory."

Rambus Inc., a premier chip and silicon IP provider making data faster and safer, today announced the availability of its PCI Express (PCIe) 6.0 Interface Subsystem comprised of PHY and controller IP. The Rambus PCIe Express 6.0 PHY also supports the latest version of the Compute Express Link (CXL) specification, version 3.0. "The rapid advancement of AI/ML and data-intensive workloads is driving the continued evolution of data center architectures requiring ever higher levels of performance," said Scott Houghton, general manager of Interface IP at Rambus. "The Rambus PCIe 6.0 Interface Subsystem supports the performance requirements of next-generation data centers with premier latency, power, area and security."

The Rambus PCIe 6.0 Interface Subsystem delivers data rates of up to 64 Gigatransfers per second (GT/s) and has been fully optimized to meet the needs of advanced heterogenous computing architectures. Within the subsystem, the PCIe controller features an Integrity and Data Encryption (IDE) engine dedicated to protecting the PCIe links and the valuable data transferred over them. On the PHY side, full support for CXL 3.0 is available to enable chip-level solutions for cache-coherent memory sharing, expansion and pooling.

-Rambus Inc., a provider of industry-leading chips and silicon IP making data faster and safer, today announced it has signed an agreement to acquire Hardent, Inc. ("Hardent"), a leading electronic design company. This acquisition augments the world-class team of engineers at Rambus and accelerates the development of CXL processing solutions for next-generation data centers. With 20 years of semiconductor experience, Hardent's world-class silicon design, verification, compression, and Error Correction Code (ECC) expertise provides key resources for the Rambus CXL Memory Interconnect Initiative.

"Driven by the demands of advanced workloads like AI/ML and the move to disaggregated data center architectures, industry momentum for CXL-based solutions continues to grow," said Luc Seraphin, president and CEO of Rambus. "The addition of the highly-skilled Hardent design team brings key resources that will accelerate our roadmap and expand our reach to address customer needs for next-generation data center solutions." "The Rambus culture and track record of technology leadership is an ideal fit for Hardent," said Simon Robin, president and founder of Hardent. "The team is looking forward to joining Rambus and is excited to be part of a global company advancing the future of data center solutions." In addition, Hardent brings complementary IP and services to the Rambus silicon IP portfolio, expanding the customer base and design wins in automotive and consumer electronic applications. The transaction is expected to close in the second calendar quarter of 2022 and will not materially impact results.

Rambus Inc., a premier chip and silicon IP provider making data faster and safer, today announced the availability of its PCI Express (PCIe ) 6.0 Controller. The PCIe specification is the interconnect of choice across a broad landscape of data-intensive markets including data center, AI/ML, HPC, automotive, IoT, defense and aerospace. Optimized for power, area and latency, the Rambus PCIe 6.0 controller delivers data rates up to 64 Gigatransfers per second (GT/s) for high-performance applications. In addition, the controller provides state-of-the-art security with an Integrity and Data Encryption (IDE) engine that monitors and protects PCIe links against physical attacks.

"The rapid advancement of AI/ML and data-intensive workloads requires that we continue to provide higher data rate solutions with best-in-class latency, power and area," said Sean Fan, chief operating officer at Rambus. "As the latest addition to our portfolio of industry-leading interface IP, our PCIe 6.0 Controller offers customers an easy to integrate solution that delivers both performance and security for advanced SoCs and FPGAs."

Rambus, today announced it is now sampling its 5600 MT/s 2nd-generation RCD chip to the major DDR5 memory module (RDIMM) suppliers. This new level of performance represents a 17% increase in data rate over the first-generation 4800 MT/s Rambus DDR5 RCD. With key innovations, Rambus is able to deliver 5600 MT/s performance at lower latency and power while optimizing timing parameters for improved RDIMM margins.

"Advanced workloads are driving an insatiable demand for greater memory bandwidth," said Shane Rau, research vice president, Computing Semiconductors at IDC. "It's essential that DDR5 ecosystem players like Rambus continue to raise the bar on performance to meet the rapidly rising needs of data center applications."

Rambus Inc., a premier chip and silicon IP provider making data faster and safer, today announced the Rambus HBM3-ready memory interface subsystem consisting of a fully-integrated PHY and digital controller. Supporting breakthrough data rates of up to 8.4 Gbps, the solution can deliver over a terabyte per second of bandwidth, more than double that of high-end HBM2E memory subsystems. With a market-leading position in HBM2/2E memory interface deployments, Rambus is ideally suited to enable customers' implementations of accelerators using next-generation HBM3 memory.

"The memory bandwidth requirements of AI/ML training are insatiable with leading-edge training models now surpassing billions of parameters," said Soo Kyoum Kim, associate vice president, Memory Semiconductors at IDC. "The Rambus HBM3-ready memory subsystem raises the bar for performance enabling state-of-the-art AI/ML and HPC applications."

Rambus Inc. (NASDAQ: RMBS), a premier silicon IP and chip provider making data faster and safer, today announced it has achieved a record 4 Gbps performance with the Rambus HBM2E memory interface solution consisting of a fully-integrated PHY and controller. Paired with the industry's fastest HBM2E DRAM from SK hynix operating at 3.6 Gbps, the solution can deliver 460 GB/s of bandwidth from a single HBM2E device. This performance meets the terabyte-scale bandwidth needs of accelerators targeting the most demanding AI/ML training and high-performance computing (HPC) applications.

"With this achievement by Rambus, designers of AI and HPC systems can now implement systems using the world's fastest HBM2E DRAM running at 3.6 Gbps from SK hynix," said Uksong Kang, vice president of product planning at SK hynix. "In July, we announced full-scale mass-production of HBM2E for state-of-the-art computing applications demanding the highest bandwidth available."

Rambus, a maker of various Interface IP solutions, today announced the latest addition to its high-speed memory interface IP product portfolio in form of High Bandwidth Memory 2E (HBM2E) controller and physical layer (PHY) IP solution. The two IPs are enabling customers to completely integrate the HBM2E memory into their products, given that Rambus provides a complete solution for controlling and interfacing the memory. The design that Ramus offers can support for 12-high DRAM stacks of up to 24 Gb devices, making for up to 36 GB of memory per 3D stack. This single 3D stack is capable of delivering 3.2 Gbps over a 1024-bit wide interface, delivering 410 GB/s of bandwidth per stack.

The HBM2E controller core is DFI 3.1 compatible and has support for logic interfaces like AXI, OCP, or a custom one, so the customer can choose a way to integrate this core in their design. With a purchase of their HBM2E IP, Rambus will provide source code written in Hardware Description Language (HDL) and GDSII file containing the layout of the interface.

Rambus Inc., a premier silicon IP and chip provider making data faster and safer, today announced it has achieved industry-leading 18 Gbps performance with the Rambus GDDR6 Memory PHY. Running at the industry's fastest data rate of 18 Gbps, the Rambus GDDR6 PHY IP delivers peak performance four-to-five times faster than current DDR4 solutions and continues the company's longstanding tradition of developing leading-edge products. The Rambus GDDR6 PHY pairs with the companion GDDR6 memory controller from the recent acquisition of Northwest Logic to provide a complete and optimized memory subsystem solution.

Increased data usage in applications such as AI, ML, data center, networking and automotive systems is driving a need for higher bandwidth memory. The coming introduction of high-bandwidth 5G networks will exacerbate this challenge. Working closely with our memory partners, the Rambus GDDR6 solution gives system designers more options in selecting the memory system that meets both their bandwidth and cost requirements.

Rambus Inc. one of the world's premier technology licensing companies, today announced that the Company's Board of Directors has terminated Dr. Ron Black as Chief Executive Officer, effective immediately.

The termination follows an incident unrelated to the Company's financial and business performance in which the Board determined Dr. Black's conduct fell short of the Company's standards. Dr. Black has also resigned from his position on the Rambus Board of Directors. The Board has appointed Luc Seraphin, Senior Vice President & General Manager, Memory and Interfaces Division, as interim CEO of the Company while the Board commences a formal search to identify a new CEO.

Rambus Inc. today announced the GDDR6 (Graphics Double Data Rate) Memory PHY IP Core targeted for high-performance applications including cryptocurrency mining, artificial intelligence (AI), ADAS (advanced driver assistance systems) and networking. Leveraging almost 30 years of high-speed interface design expertise and using advanced leading-edge FinFET process nodes, the Rambus GDDR6 PHY architecture will provide the industry's highest speed of up to 16 Gbps, while utilizing established packaging and testing techniques.

"The high bandwidth delivered by GDDR6 makes it uniquely qualified to perform data-intensive applications such as HPC (high performance computing), AI, autonomous vehicles, and high-speed networking," said Luc Seraphin, SVP and general manager of the Rambus Memory and Interfaces Division. "We are excited to be the first IP provider to offer a GDDR6 PHY solution with industry-leading performance designed with power efficiency and high signal margins for these applications."

Micron Technology, Inc., a leading memory and storage provider, today announced with Rambus Inc., Northwest Logic and Avery Design, their efforts to deliver a comprehensive solution for GDDR6, the world's fastest discrete memory. This first-of-its-kind solution would enable GDDR6 use in advanced applications such as high-performance networking, autonomous vehicles, artificial intelligence and 5G infrastructure. Prior generations of GDDR memories, enabled by GPU vendors, were focused exclusively on the graphics market. While this allowed graphics and game console designs to take advantage of the significant performance advantage offered by GDDR, other applications could not because the necessary building blocks were not available.

Rambus, a company that has veered around the line of being an innovative company and a patent troll, has shed some more light on what can be expected from HBM3 memory (when it's finally available). In an investor meeting, representatives from the company shared details regarding HBM3's improvements over HBM2. Details are still scarce, but at least we know Rambus' expectations for the technology: double the memory bandwidth per stack when compared to HBM2 (4000 MB/s), and a more complex design, which leaves behind the 2.5D design due to increased height of the HBM3 memory stacks. An interesting thing to note is that Rambus is counting on HBM3 to be produced on 7 nm technologies. Considering the overall semiconductor manufacturing calendar for the 7 nm process, this should place HBM3 production in 2019, at the earliest.

HBM3 is also expected to bring much lower power consumption compared to HBM2, besides increasing memory density and bandwidth. However, the "complex design architectures" in the Rambus slides should give readers pause. HBM2 production has had some apparent troubles in reaching demand levels, with suspected lower yields than expected being the most likely culprit. Knowing the trouble AMD has had in successful packaging of HBM2 memory with the silicon interposer and its own GPUs, an even more complex implementation of HBM memory in HBM3 could likely signal some more troubles in that area - maybe not just for AMD, but for any other takers of the technology. Here's hoping AMD's woes were due only to one-off snags on their packaging partners' side, and doesn't spell trouble for HBM's implementation itself.

DDR5, the natural successor to today's DDR4 memory that brings with double the bandwidth and density versus current generation DDR4. along with delivering improved channel efficiency, is expected to be available in the market starting 2019. JEDEC, the standards body responsible for the DDR specifications, says that base DDR5 frequencies should be at around DDR5-4800 - more than double that of base DDR4's 2133, but a stone throw away from today's fastest (and uber, kidney-like-expensive) 4600 MHz memory kits from the likes of G.Skill and Corsair.

DDR5 is expected to support data rates up to 6.4 Gb/s delivering 51.2 GB/s max, up from 3.2 Gb/s and 25.6 GB/s for today's DDR4. The new version will push the 64-bit link down to 1.1V and burst lengths to 16 bits from 1.2V and 8 bits. In addition, DDR5 lets voltage regulators ride on the memory card rather than the motherboard. CPU vendors are also expected to expand the number of DDR channels on their processors from 12 to 16, which could drive main memory sizes to 128 GB from 64 GB today. Whether this will be good for end-users in relation to DDR5 memory prices remains open for debate; however, considering the rampant memory prices this side of 2017, chances are it won't be unless supply increases considerably.