In a bid to maximize utilization of its own semiconductor foundry for manufacturing larger, more profitable processors, Intel could be look at contracting TSMC to manufacture certain processors based on its low-power CPU microarchitectures, according to a new Intel job posting discovered by Komachi Ensaka. The job description for a position in Intel's Bengaluru facility, speaks of a "QAT Design Integration Engineer" who would play a role in the "development and integration of CPM into Atom and Xeon-based SoC on Intel and TSMC process."

QAT is a hardware feature that accelerates cryptography and data-compression workloads. Since the Xeon part in this sentence is referenced next to SoC, Intel could be referring to Xeon processors based on low-power cores, such as "Snow Ridge," which uses "Tremont" CPU cores. The decision to go with TSMC could also be driven by the 5G infrastructure hardware gold rush awaiting the likes of Intel across dozens of new markets, particularly those averse to buying hardware from Huawei.

Intel on Thursday was hit by a massive data-breach, with someone on Twitter posting links to an archive that contains the dump of the breach - a 20-gigabyte treasure chest that includes - but not limited to - Intel Management Engine bringup guides, flashing tools, samples; source code of Consumer Electronics Firmware Development Kit (CEFDK); silicon and FSP source packages for various platforms; an assortment of development and debugging tools; Simics simulation for "Rocket Lake S" and other platforms; a wealth of roadmaps and other documents; shcematics, documents, tools, and firmware for "Tiger Lake," Intel Trace Hub + decoder files for various Intel ME versions; "Elkhart Lake" silicon reference and sample code; Bootguard SDK, "Snow Ridge" simulator; design schematics of various products; etc.

The most fascinating part of the leak is the person points to the possibility of Intel laying backdoors in its code and designs - a very tinfoil hat though likely possibility in the post-9/11 world. Intel in a comment to Tom's Hardware denied that its security apparatus had been compromised, and instead blamed someone with access to this information for downloading the data. "We are investigating this situation. The information appears to come from the Intel Resource and Design Center, which hosts information for use by our customers, partners and other external parties who have registered for access. We believe an individual with access downloaded and shared this data," a company spox said.

A leaked Intel internal slide surfaced on Chinese social networks, revealing five new products the company will build on its 10 nm silicon fabrication process. These include the "Alder Lake" heterogenous desktop processor, "Tiger Lake" mobile processor, "Ice Lake" based Xeon Scalable enterprise processors, DG1 discrete GPU, and "Snow Ridge" 5G base-station SoC. Some, if not all of these products, will implement Intel's new 10 nm+ silicon fabrication node that is expected to go live within 2020.

"Alder Lake" is a desktop processor that implements Intel's new heterogenous x86 core design that's making its debut with "Lakefield." The chip features up to 8 larger "Willow Cove" or "Golden Cove" CPU cores, and up to 8 smaller "Tremont" or "Gracemont" cores. This 8-big/8-small combo lets the chip achieve TDP targets around 80 Watts. Next up is "Tiger Lake," Intel's next-generation mobile processor family succeeding "Ice Lake." This microarchitecture implements "Willow Cove" CPU cores in a homogeneous setup, alongside Xe architecture based integrated graphics. "Ice Lake-SP" is Intel's next enterprise architecture that places mature "Sunny Cove" CPU cores in extreme core-count dies. Lastly, there's "Snow Ridge," an SoC purpose built for 5G base-stations. Image quality notwithstanding, these slides don't appear particularly new, and it's likely that COVID-19 has destabilized the roadmap. For instance, "Alder Lake," and "Ice Lake-SP" are expected to be 10 nm++ chips, a node that doesn't go live before 2021.

Intel's next-generation Pentium Silver "Snow Ridge" SoC, featuring "Tremont" CPU cores, could see the debut of an L3 cache to the segment. Intel CPU cores in this segment, such as the "Goldmont Plus," only feature shared L2 caches across 4-core modules. The introduction of L3 cache was indicated by a new performance counter "MEM_LOAD_UOPS_RETIRED_L3_HIT," with a description clearly mentioning a "level 3 cache." The introduction of L3 cache as the SoC's LLC (last level cache) could mean Intel is trying to improve inter-component communication by introducting the L3 cache as "town-square" for the various components of the SoC, such as the CPU cores, the iGPU, and the integrated chipset. The company could deploy a ring-bus interconnect that has ring-stops at the various components, and slices of this L3 cache. Intel is building the "Snow Ridge" silicon on its swanky new 10 nm silicon fabrication process, and the chip could see a 2020 debut targeting network infrastructure devices.