Cadence Design Systems, Inc., a leader in global electronic design automation, and Intel Corporation, a world leader in computing innovation, today announced that the companies are collaborating to support Intel's 14 nm Tri-Gate process technology to enable customers of Intel Custom Foundry.

Cadence and Intel have together enabled the custom/analog flow, including Spectre APS, Virtuoso Schematic Editor, Virtuoso Layout Suite and Virtuoso Analog Design Environment for the 14nm Tri-Gate process. The companies are also collaborating on the development of the Cadence digital flow featuring Encounter Digital Implementation System, QRC Extraction Solution, and Tempus Timing Signoff Solution. Using these design flows, customers can leverage the power, performance and area benefits of Intel's 14 nm process technology.

Intel Corporation today took the wraps off its brand new, low-power, high-performance microarchitecture named Silvermont. The technology is aimed squarely at low-power requirements in market segments from smartphones to the data center. Silvermont will be the foundation for a range of innovative products beginning to come to market later this year, and will also be manufactured using the company's leading-edge, 22nm Tri-Gate SoC manufacturing process, which brings significant performance increases and improved energy efficiency.

"Silvermont is a leap forward and an entirely new technology foundation for the future that will address a broad range of products and market segments," said Dadi Perlmutter, Intel executive vice president and chief product officer. "Early sampling of our 22nm SoCs, including "Bay Trail" and "Avoton" is already garnering positive feedback from our customers. Going forward, we will accelerate future generations of this low-power microarchitecture on a yearly cadence."

Tabula Inc., advancing programmable logic solutions for network infrastructure systems, today confirmed previous speculation that it is implementing a family of 3PLD products manufactured by Intel using its advanced 22 nm manufacturing process featuring 3-D Tri-Gate transistors and co-optimized packaging technology. This is made possible by a manufacturing access agreement between Tabula Inc., and Intel Custom Foundry, a division of the Technology and Manufacturing Group of Intel Corporation.

The 3PLD family will be based on Tabula's 3D Spacetime architecture and will deliver high-performance, cost-effective solutions for network infrastructure systems requiring high-bandwidth data flows such as Switches, Routers, Packet Inspection appliances, and other high-performance systems. The combination of process and architecture will allow Tabula to produce high-performance programmable circuits that consume significantly less chip area than circuits implemented with traditional FPGA fabrics.

Making silicon chips is not easy, requiring hugely expensive fabs, with massive clean-room environments and at every process shrink, the complexity and difficulty of making the things goes up significantly. It looks like TSMC and GlobalFoundries are both having serious yield problems with their 28 nm process nodes, according to Mike Bryant, technology analyst at Future Horizons and this is causing a rash of non-working wafers - to the point of having nothing working with some chip designs submitted for production. It seems that the root cause of these problems are to do with the pressures of bringing products to market, rather than an inherent problem with the technology; it just takes time that they haven't got to iron out the kinks and they're getting stuck: "Foundries have come under pressure to release cell libraries too early - which end up with designs that don't work," Bryant said. In an effort to try and be seen to treat every customer equally, TSMC is attempting to launch ten 28 nm designs from seven companies, but it's not working out too well: "At 45-nm, only NVIDIA was affected. At 28-nm any problems for TSMC will be problems for many customers" said Bryant.

Welcome to the TechPowerUp 2011 PC technology Christmas special. We hope that you will enjoy reading it while tucking into your turkey, Christmas presents and a little too much wine... In this article, we go through the technology of 2011 that has had the most significance, the most impact and was generally the most talked about. It's not necessarily the best tech of 2011 which is the most significant though, since lemons can be just as significant as the ground-breakers in how they fail to deliver - and the backlash that goes with it.

January: Intel Sandy Bridge i5 & i7

Released on January 9th, the new Intel Core i5 & i7 processors were based on Intel's second generation Core architecture built on a 32 nm production process (HEXUS review). They included an IGP (Integrated Graphics Processor) physically on the same piece of silicon along with HyperThreading. These new dual and quad core processors soundly beat all previous generations of Intel processors in terms of processing performance, heat, power use, features and left AMD in the dust. Therefore, Intel badly needed some competition from AMD and unless you have been living under a rock, you will know how that turned out in October with the launch of Bulldozer. Sandy Bridge was a sound win and is generally considered to be the only architecture worth considering at this point. The i5-2500K is currently at the sweet spot of price/performance. It comes at a stock speed of 3.3 GHz, but typically overclocks to an amazing 4.5 - 5 GHz with a decent air cooler and without too much difficulty in getting there. Models in the budget i3 range were released at various times later. See this Wikipedia article for details.

Micron Technology, one of the biggest DRAM companies, has announced that it's working the JEDEC standards organization for computer memory, to standardize a new DRAM interface and die-stacking technology called three-dimensional stacking, or 3DS, which may be incorporated into the upcoming DDR4 standard. X-bit labs has a nice summary of how 3DS works:

The idea behind 3DS is to use specially designed and manufactured master-and-slave DRAM die, with only the master die interfacing with the external memory controller. 3DS technology uses optimized DRAM die, single DLL per stack, reduced active logic, single shared external I/O, improved timing, and reduced load to the external world. This combination of features can improve timing, bus speeds, and signal integrity while lowering both power consumption and system overhead for next-generation modules, according to Micron.