AYANEO has officially revealed its latest handheld gaming console, dubbed the AYANEO 3. The company has teased the handheld multiple times in the past, while refraining from sharing any specifications regarding the same. Now, however, the company has detailed the internals for its new flagship handheld along with a few extra details.

The AYANEO 3 appears to be powered exclusively by AMD APUs, with Intel's Lunar Lake options nowhere to be found. Interested buyers will get to choose between either the Ryzen AI 9 HX 370 "Strix Point" APU, or the Ryzen 7 8840U "Hawk Point" APU. The "Strix Point" option happens to be AMD's latest and greatest, packing 4 Zen 5 and 8 Zen 5c cores, while the "Hawk Point" option sports 8 Zen 4 cores only.

AMD's answer to Intel's "Lunar Lake" is here. According to Olrak29, who discovered a strange entry on the OpenBenchmark benchmarking suite made by Phoronix, we have preliminary information on AMD's "Krackan / Kraken Point" APU. Spotted in the benchmark trials is the "100-000000713" model, which corresponds to an eight-core, sixteen-threaded CPU with four regular Zen 5 and four smaller (but not less potent) Zen 5c cores clocked at 3.95 GHz. Do note that this is just an engineering sample in the wild, so final clock speeds will depend mainly on AMD and its OEMs, given by TDP they plan to support with Kraken Point.

Accompanying the 8C/16T CPU configuration is the 32 GB of LPDDR5X memory from SK Hynix. According to the benchmark reading, four 8 GB modules were present, so we expect it to be on the system board, unlike on-chip like Intel does with Lunar Lake. The memory is running at 8000 MT/s, which is a 500 MT/s improvement over Strix Point and slower than its competitor, Lunar Lake, which has LPDDR5X running at 8533 MT/s. Lastly, the Krackan / Kraken Point APU has been spotted with eight RDNA 3.5 Compute Units. Where this exactly lands in AMD's product stack is still unclear. We expect to hear more about it as we enter 2025, so by then, remain patient until the next leak.

The second generation of AMD Ryzen Z-series processors for handheld gaming consoles, will be led by the Ryzen Z2 Extreme. There will also be an affordable Ryzen Z2 (non-Extreme). We've known for some time that the Z2 Extreme is based on the 4 nm "Strix Point" monolithic silicon, with some optimization (the highest bins to facilitate the best energy efficiency); but now we have a few more details thanks to a leak by Golden Pig Upgrade. AMD's engineering effort with the Z2 Extreme will be to give the console the most generational performance uplift from the iGPU, rather than the CPU.

The "Strix Point" silicon features a significantly updated iGPU from the previous-generation "Phoenix." It's based on the more efficient RDNA 3.5 graphics architecture, which is better optimized for LPDDR5 memory; and comes with 16 compute units (CU), compared to 12 on the "Phoenix." The Ryzen Z2 Extreme will come with all 16 CU enabled. The CPU is where some interesting changes are planned. The "Strix Point" silicon features a dual-CCX CPU, one of these contains four "Zen 5" CPU cores sharing a 16 MB L3 cache, while the other features eight "Zen 5c" cores sharing an 8 MB L3 cache. For the Ryzen Z2 Extreme, AMD is going with an odd 3+5 core configuration. What this means is that the Ryzen Z2 Extreme will have 3 "Zen 5" cores, and 5 "Zen 5c" cores. The L3 cache on the CCX with "Zen 5" cores has been reduced to 8 MB in size. On paper, this is still an 8-core/16-thread CPU with 16 MB of L3 cache (same as "Phoenix,") but now you know that there's more going on.

AMD has unveiled its latest EPYC processors, codenamed "Turin," featuring Zen 5 and Zen 5C dense cores. Phoronix's thorough testing reveals remarkable advancements in performance, efficiency, and value. The new lineup includes the EPYC 9575F (64-core), EPYC 9755 (128-core), and EPYC 9965 (192-core) models, all showing impressive capabilities across various server and HPC workloads. In benchmarks, a dual-socket configuration of the 128-core EPYC 9755 Turin outperformed Intel's dual Xeon "Granite Rapids" 6980P setup with MRDIMM-8800 by 40% in the geometric mean of all tests. Surprisingly, even a single EPYC 9755 or EPYC 9965 matched the dual Xeon 6980P in expanded tests with regular DDR5-6400. Within AMD's lineup, the EPYC 9755 showed a 1.55x performance increase over its predecessor, the 96-core EPYC 9654 "Genoa". The EPYC 9965 surpassed the dual EPYC 9754 "Bergamo" by 45%.

These gains come with improved efficiency. While power consumption increased moderately, performance improvements resulted in better overall efficiency. For example, the EPYC 9965 used 32% more power than the EPYC 9654 but delivered 1.55x the performance. Power consumption remains competitive: the EPYC 9965 averaged 275 Watts (peak 461 Watts), the EPYC 9755 averaged 324 Watts (peak 500 Watts), while Intel's Xeon 6980P averaged 322 Watts (peak 547 Watts). AMD's pricing strategy adds to the appeal. The 192-core model is priced at $14,813, compared to Intel's 128-core CPU at $17,800. This competitive pricing, combined with superior performance per dollar and watt, has resonated with hyperscalers. Estimates suggest 50-60% of hyperscale deployments now use AMD processors.

AMD (NASDAQ: AMD) today announced the availability of the 5th Gen AMD EPYC processors, formerly codenamed "Turin," the world's best server CPU for enterprise, AI and cloud. Using the "Zen 5" core architecture, compatible with the broadly deployed SP5 platform and offering a broad range of core counts spanning from 8 to 192, the AMD EPYC 9005 Series processors extend the record-breaking performance and energy efficiency of the previous generations with the top of stack 192 core CPU delivering up to 2.7X the performance compared to the competition.

New to the AMD EPYC 9005 Series CPUs is the 64 core AMD EPYC 9575F, tailor made for GPU powered AI solutions that need the ultimate in host CPU capabilities. Boosting up to 5 GHz, compared to the 3.8 GHz processor of the competition, it provides up to 28% faster processing needed to keep GPUs fed with data for demanding AI workloads.

AMD is readying a major update to its category-defining Ryzen Z-series SoCs, with the new Ryzen Z2. Designed for handheld game consoles, the Ryzen Z-series chips are typically power-optimized variants of its mobile processors designed for ultra-low board footprint, allowing PC OEMs to build handheld game consoles with them. Facing competition from Intel's upcoming Core Ultra 200V "Lunar Lake-MX" SoCs in this segment, AMD is readying the Ryzen Z2 chip. The Z2 is based on the 4 nm "Strix Point" silicon, which gives it a significantly updated iGPU, as well as a higher core-count CPU.

Perhaps the biggest sub-system performance uplift console designers can expect from the Ryzen Z2 is graphics—AMD has given the "Strix Point" a larger iGPU with 16 compute units in place of 12 on "Phoenix," which is a 33% increase in just numerical terms. Then there's also the update to the newer RDNA 3.5 graphics architecture, which incorporates several architecture-level performance and battery-efficiency improvements. It's also better optimized for LPDDR5 memory. With CPU, AMD has given "Strix Point" a heterogeneous multicore setup with four "Zen 5" and eight "Zen 5c" cores. At this point, we don't know if all 12 cores are enabled on the Z2. ASUS is designing its next generation of ROG Ally consoles powered by the Ryzen Z2, and its designers hint that the console should be able to offer over 1 hour of "Black Myth: Wukong" gameplay on a full charge of battery—something current-gen ROG Ally X powered by the Z1 doesn't.

The first die shot of AMD's new 4 nm "Strix Point" mobile processor surfaced, thanks to an enthusiast on Chinese social media. "Strix Point" is a significantly larger die than "Phoenix." It measures 12.06 mm x 18.71 mm (L x W), compared to the 9.06 mm x 15.01 mm of "Phoenix." Much of this die size increase comes from the larger CPU, iGPU, and NPU. The process has been improved from TSMC N4 on "Phoenix" and its derivative "Hawk Point," to the newer TSMC N4P node.

Nemez (GPUsAreMagic) annotated the die shot in great detail. The CPU now has 12 cores spread across two CCX, one of which contains four "Zen 5" cores sharing a 16 MB L3 cache; and the other with eight "Zen 5c" cores sharing an 8 MB L3 cache. The two CCXs connect to the rest of the chip over Infinity Fabric. The rather large iGPU takes up the central region of the die. It is based on the RDNA 3.5 graphics architecture, and features 8 workgroup processors (WGPs), or 16 compute units (CU) worth 1,024 stream processors. Other key components include four render backends worth 16 ROPs, and control logic. The GPU has its own 2 MB of L2 cache that cushions transfers to the Infinity Fabric.

Since its reveal last week, we got a slightly more technical deep-dive from AMD on its two upcoming processors—the "Strix Point" silicon powering its Ryzen AI 300 series mobile processors; and the "Granite Ridge" chiplet MCM powering its Ryzen 9000 desktop processors. We present a closer look into the "Strix Point" SoC in this article. It turns out that "Strix Point" takes a significantly different approach to heterogeneous multicore than "Phoenix 2." AMD gave us a close look at how this works. AMD built the "Strix Point" monolithic silicon on the TSMC N4P foundry node, with a die-area of around 232 mm².

The "Strix Point" silicon sees the company's Infinity Fabric interconnect as its omnipresent ether. This is a point-to-point interconnect, unlike the ringbus on some Intel processors. The main compute machinery on the "Strix Point" SoC are its two CPU compute complexes (CCX), each with a 32b (read)/16b (write) per cycle data-path to the fabric. The concept of CCX makes a comeback with "Strix Point" after nearly two generations of "Zen." The first CCX contains the chip's four full-sized "Zen 5" CPU cores, which share a 16 MB L3 cache among themselves. The second CCX contains the chip's eight "Zen 5c" cores that share a smaller 8 MB L3 cache. Each of the 12 cores has a 1 MB dedicated L2 cache.

AMD in its architecture deep-dive Q&A session with the press, confirmed that the "Zen 5" and "Zen 5c" cores on the "Strix Point" silicon only feature 256-bit wide FPU data-paths, unlike the "Zen 5" cores in the "Granite Ridge" Ryzen 9000 desktop processors. "The Zen 5c used in Strix has a 256-bit data-path, and so does the Zen 5 used inside of Strix," said Mike Clark, AMD corporate fellow and chief architecture of the "Zen" CPU cores. "So there's no delta as you move back and forth [thread migration between the Zen 5 and Zen 5c complexes] in vector throughput," he added.

It doesn't seem like AMD disabled a physically available feature, but rather, the company developed a variant of both the "Zen 5" and "Zen 5c" cores that physically lack the 512-bit data-paths. "And you get the area advantage to be able to scale out a little bit more," Clark continued. This suggests that the "Zen 5" and "Zen 5c" cores on "Strix Point" are physically smaller than the ones on the 4 nm "Eldora" 8-core CCD that is featured in "Granite Ridge" and some of the key models of the upcoming 5th Gen EPYC "Turin" server processors.

AMD is about give the new "Zen 5" microarchitecture a near-simultaneous launch across both its client segments—desktop and mobile. The desktop front is held by the Ryzen 9000 "Granite Ridge" Socket AM5 processors; while Ryzen AI 300 "Strix Point" powers the company's crucial effort to capture Microsoft Copilot+ AI PC market share. We recently did a technical deep-dive on the two. HardwareLuxx.de scored two important bits of specs for both processors in its Q&A interaction with AMD—die sizes and transistor counts.

To begin with, "Strix Point" is a monolithic silicon, which is confirmed to be built on the TSMC N4P foundry node (4 nm). This is a slight upgrade over the N4 node that the company built its previous generation "Phoenix" and "Hawk Point" processors on. The "Strix Point" silicon measures 232.5 mm² in area, which is significantly larger than the 178 mm² of "Hawk Point" and "Phoenix." The added die area comes from there being 12 CPU cores instead of 8, and 16 iGPU compute units instead of 12; and a larger NPU. There are many other factors, such as the larger 24 MB CPU L3 cache; and the sizes of the "Zen 5" and "Zen 5c" cores themselves.

CPUID this week released the latest version of CPU-Z, and its change-log confirms the core-configurations of upcoming AMD Ryzen AI 300-series "Strix Point" processor SKUs. On paper, "Strix Point" packs a 12-core CPU based on the latest "Zen 5" microarchitecture, but there's more to this number. We've known since June 2024 that the chip has a heterogeneous multicore configuration of four full-sized "Zen 5" cores, and eight compacted "Zen 5c" cores. Only the "Zen 5" cores can reach the maximum boost frequencies rated for the chip, while the "Zen 5c" cores go a few notches above the base frequency, although it's expected that the gap in boost frequencies between the two core types is expected to slightly narrow compared to that between the "Zen 4" and "Zen 4c" cores in chips such as the "Phoenix 2."

The series is led by the AMD Ryzen AI 9 HX 375, an enthusiast segment chip that maxes out all 12 cores on the chip—that's 4x "Zen 5" and 8x "Zen 5c." This model is closely followed by the Ryzen AI 9 365, which AMD marked in its presentations as being simply a 10-core/20-thread chip. We're now learning that it has 4x "Zen 5" and 6x "Zen 5c," meaning that AMD hasn't touched the counts of its faster "Zen 5" cores. It's important to note here that "Zen 5c" is not an E-core. It supports SMT, and at base frequency, it has an identical IPC to "Zen 5." It also supports the entire ISA that "Zen 5" does.

ASUS announced a press event on July 17 to launch at least nine notebook designs powered by AMD Ryzen AI 300 series "Strix Point" mobile processors. All these notebooks are AI PCs that meet Microsoft Copilot+ requirements. Each of the 9 designs will have several variants based on the processor model, discrete graphics, and other hardware differentiators, making up dozens of individual SKUs. The AMD "Strix Point" mobile processor is based on a 4 nm monolithic die. It combines a 12-core/24-thread CPU based on a combination of "Zen 5" and "Zen 5c" cores, a 50 TOPS-class NPU, and a powerful iGPU based on the RDNA 3.5 graphics architecture, with 16 compute units.

Among the notebook designs ASUS plans to announce on July 17 are the ROG Zephyrus G16 (GA605), the TUF Gaming A14 (FA401), the TUF Gaming A16 (FA608), the Zenbook S16 (UM5606), Vivobook S14 (M5406), Vivobook S16 (M5506 and M5606), ProArt P16 (HN7606) and ProArt PX13 (HN7306). With these, ASUS is covering pretty much all its notebook market segments, including enthusiast gaming, performance gaming, boutique ultraportability, mainstream, and creative professional.

The top-spec AMD Ryzen AI 9 300 series "Strix Point" processor, the Ryzen AI 9 HX 370, is expected to post a 20% performance improvement over both the CPU and integrated graphics fronts, over its predecessor, the Ryzen 9 8945HS "Hawk Point," according to leak by Golden Pig Upgrade. On the CPU front, the HX 370 packs a 12-core/24-thread CPU based on a combination of four "Zen 5" and eight "Zen 5c" cores. The single-thread performance gains on the basis of the "Zen 5" microarchitecture's generational IPC increase, besides higher clock speeds; while the multithreaded performance increases on account on more cores. This performance increase isn't linearly scaling with the 50% increase in core-count.

On "Hawk Point," all eight cores are "Zen 4," capable of boosting to high frequencies, with two of them being marked as CPPC preferred cores, capable of boosting the highest. On "Strix Point," however, only four cores are based on the "Zen 5" architecture and capable of boosting to high frequency bands; while the other eight are "Zen 5c," which don't boost as high. While the IPC of "Zen 5c" is identical to "Zen 5," the fact that it doesn't boost as high, means that the generational multithreaded performance gain from the core-count increase is expected to be closer to 20%, with Golden Pig Upgrade talking about a Cinebench R23 nT score of over 20000 points, with "Hawk Point" scoring around 16000 points.

AMD on Monday launched its Ryzen AI 300 line of mobile processors based on the 4 nm "Strix Point" monolithic silicon. This chip was described by AMD as having a maximum CPU core configuration of 12-core/24-thread, which would be a neat 50% increase in core-counts over the previous generation; but there's more to it. Although "Strix Point" implements "Zen 5," not all 12 CPU cores on the silicon are the regular variant of "Zen 5." The chip physically has four "Zen 5" cores, and eight "Zen 5c" compact cores. Nemez (GPUsAreMagic) attempted to annotate the "Strix Point" die based a high-resolution photo by System360Cheese from AMD's Computex keynote; and there are some interesting findings.

The annotation reveals that the four regular "Zen 5" cores, each with a 1 MB dedicated L2 cache, share a 16 MB L3 cache. The eight "Zen 5c" cores, on the other hand, appear to share a smaller 8 MB L3 cache, in what could be a separate CCX. They each have a 1 MB L2 cache, too. The "Zen 5c" cores have the same IPC as the "Zen 5" cores when measured with common INT and FP benchmarks that don't move a lot of data; however, it could lag behind in workloads with a lot of streaming data. What's more, the previous generation "Zen 4c" cores were traditionally limited to lower frequencies than regular "Zen 4" cores, as the physically compacted cores couldn't hold onto higher core voltages. If that's the case with "Zen 5c," then what we're really looking at with "Strix Point" is an interesting hybrid core setup with eight high-IPC efficiency cores.

AMD today launched its Ryzen AI 300 series mobile processors, codenamed "Strix Point." These chips implement a combination of the AMD "Zen 5" microarchitecture for the CPU cores, the XDNA 2 architecture for its powerful new NPU, and the RDNA 3+ graphics architecture for its 33% faster iGPU. The new "Zen 5" microarchitecture provides a 16% generational IPC uplift over "Zen 4" on the backs of several front-end enhancements, wider execution pipelines, more intra core bandwidth, and a revamped FPU that doubles performance of AI and AVX-512 workloads. AMD didn't go in-depth with the microarchitecture, but the broad points of "Zen 5" are detailed in our article for the Ryzen 9000 "Granite Ridge" desktop processors. Not only is AMD using these faster "Zen 5" CPU cores, but also increased the CPU core count by 50%, for a maximum of 12-core/24-thread.

The "Strix Point" monolithic silicon is built on the 4 nm foundry node, and packs a CPU core complex (CCX) with 12 CPU cores, four of these are "Zen 5," which can achieve the highest possible boost frequencies, the other eight are "Zen 5c" cores that feature an identical IPC and the full ISA, including support for SMT; but don't boost as high as the "Zen 5" cores. AMD is claiming a productivity performance increase ranging between 4% and 73% for its top model based in the series, when compared to Intel's Core Ultra 9 185H "Meteor Lake" processor. The iGPU sees its compute unit (CU) count go all the way up to 16 from 12 in the previous generation, and this yields a claimed 33% increase in iGPU gaming performance compared to the integrated Arc graphics of the Core Ultra 9 185H. Lastly, the XDNA 2 NPU sees more that triple the AI inference performance to 50 AI TOPS, compared to the 16 TOPS of the Ryzen 8040 "Hawk Point" processor, and 12 TOPS of Core Ultra "Meteor Lake." This makes the processor meet Microsoft's Copilot+ AI PC requirements.

AMD's future "Zen 6" CPU microarchitecture is rumored to cram up to 32 cores per CCD (CPU complex die), or the common client/server chiplet with the CPU cores, according to Kepler_L2, a reliable source with hardware leaks. At this point it's not clear if they are referring to the regular "Zen 6" CPU core, or the physically compacted "Zen 6c" core meant for high core-count cloud server processors. The current pure "Zen 4c" CCD found in EPYC "Bergamo" processor packs 16 cores across two 8-core CCX (CPU core complexes) that share a 16 MB L3 cache among the 8 cores within the CCX. The upcoming "Zen 5c" CCD will pack 16 cores, but in a single 16-core CCX that shares 32 MB of L3 cache among the 16 cores for improved per-core cache access. "Zen 6" is expected to double this to 32 cores per CCD.

The 32-core CCD powered by "Zen 6" (likely Zen 6c), might take advantage of process improvements to double the core-count. At this point, it's not clear if this jumbo CCD features a single large CCX with all 32 cores sharing a large L3 cache; or if it's using two 16-core CCX that shares, say, 32 MB of L3 cache among the 16 cores. What's clear with this leak, though, is that AMD is looking to continue ramping up CPU core counts per socket. Data-centers and cloud customers seem to love this, and AMD is the only x86 processor maker in a serious competition with Arm-based server processor manufacturers such as Ampere, to increase significantly increase core counts per socket with each generation.

AMD is reportedly building its upcoming "Zen 5" and "Zen 5c" CPU Core Dies (CCDs) on two different foundry nodes, a report by Chinese publication UDN, claims. The Zen 5 CCD powering the upcoming Ryzen "Granite Ridge" desktop processors, "Fire Range" mobile processors, and EPYC "Turin" server processors, will be reportedly built on the 4 nm EUV foundry node, a slightly more advanced node than the current 5 nm EUV the company is building "Zen 4" CCDs on. The "Zen 5c" CCD, or the chiplet with purely "Zen 5c" cores in a high density configuration; on the other hand, will be built on an even more advanced 3 nm EUV foundry node, the report says. Both CCDs will go into mass production in Q2-2024, with product launches expected across the second half of the year.

The "Zen 5c" chiplet has a mammoth 32 cores spread across two CCXs of 16 cores, each. Each CCX has 16 cores sharing a 32 MB L3 cache. It is to cram these 32 cores, each with 1 MB of L2 cache; and a total of 64 MB of L3 cache, that AMD could be turning to the 3 nm foundry node. Another reason could be voltages. If "Zen 4c" is anything to go by, the "Zen 5c" core is a highly compacted variant of "Zen 5," which operates at a lower voltage band than its larger sibling, without any change in IPC or instruction sets. The decision to go with 3 nm could be a move aimed at increasing clock speeds at those lower voltages, in a bid to generationally improve performance using clock speeds, besides IPC and core count. The EPYC processor with "Zen 5c" chiplets will feature no more than six such large CCDs, for a maximum core count of 192. The regular "Zen 5" CCD has just 8 cores in a single CCX, with 32 MB of L3 cache shared among the cores; and TSV provision for 3D Vertical Cache, to increase the L3 cache in special variants.

AMD's next generation Ryzen mobile processor family is undergoing a significant re-positioning of IP within its product stack, as the company introduces the new "elite experience" segment. The "Fire Range" mobile processor is a direct successor to "Dragon Range" MCM, with two 8-core "Zen 5" chiplets. It is essentially a BGA package of the desktop "Granite Ridge" processor, and comes with up to 16 "Zen 5" cores, for flagship gaming notebooks and mobile workstations. A segment below the current "Dragon Range" is the current "Hawk Point" silicon, driving premium experiences. There is a rather large CPU performance gap between the two, as would be the case between the upcoming "Fire Range" and "Kraken Point," which is why AMD is creating the "elite experience" segment, and filling it with "Strix Halo" and "Strix Point," which will square off against Core Ultra 7 and Core Ultra 9 processors, as well as certain HX-segment 14th Gen Core mobile processors. "Strix Point" has a significant core-count increase to 12, along with a large iGPU. We've extensively covered "Strix Point" in our older article, but now we have more information on the elusive "Kraken Point."

"Kraken Point" is codename for AMD's next-generation monolithic mobile processor silicon being designed to power Ryzen processor SKUs competing against the bulk of Intel Core Ultra 5 and Core Ultra 7 SKUs. This chip will be built on a refined 4 nm EUV node by TSMC, and will be monolithic. Its most interesting aspect is the CPU complex. It reportedly features a combination of four regular "Zen 5" cores, and four "Zen 5c" low power cores. All eight cores will likely share a single CCX, which means they share a common L3 cache, which enables easy movement of threads between the two kinds of cores, without having to make round-trips to the DRAM.

Everest (@Olrak29_) has kept track of many AMD processor families over the past couple of years—his latest insight provides an early look at the alleged internal makeup of Team Red's "Kraken Point" APU series. The rumor mill has designated these next-gen mobile processors as 2025 follow-ups to the recently launched Ryzen 8040 "Hawk Point" family of mainstream laptop APUs. The tipster's initial social media post only mentioned the presence of both Zen 5 and Zen 5c cores within Kraken Point processors, but he later clarified that a total of eight cores would include four large units and four smaller types. TPU's past coverage of Kraken Point pointed to rumors of an 8-core, 16-thread configuration, but leaked slides (from late 2023) did not mention the integration of efficiency-tuned Zen 5c "Prometheus" cores, along with presumed Zen 5 "Nirvana" cores.

Everest's continuous flow of insider information reveals that "Kraken Point" shares many "Hawk Point" traits—four workgroup processors (WGP) could be present on final retail products, granting eight compute units (8 CUs in total). He responded to a query regarding AMD's choice of integrated graphics technology—the succinct answer being RDNA 3.5. Past leaks allege that XDNA 2 will drive the NPU side of things—offering a performance range of around 45 to 50 TOPS. The Kraken Point APU is believed to be sticking with a safe monolithic die design, manufactured on a non-specific 4 nm process. Team Red is rumored to be in TSMC's order books for all sorts of next generation silicon.

AMD released its latest PMC (power management controller) driver patches for the Linux kernel, which reference a yet unreleased "Family 1Ah" processors. Phoronix believes this is the first reference to AMD's next generation "Zen 5" microarchitecture in the PMC driver. We've already seen AMD EPYC "Turin" server processors based on "Zen 5" in the flesh, and it's likely that AMD is handing these out to some of its biggest data-center customers for testing and evaluation, before giving them some final touches and green-lighting mass-production in 2024. The patches themselves are barely two new lines of code, and talk about a new sleep state called "s2idle." This is a software-defined system sleep state. The EPYC "Turin" processor comes in two packages, one with up to 128 "Zen 5" cores, and another with up to 192 "Zen 5c" cores for cloud applications.

AMD's upcoming server processor, the 5th Gen EPYC "Turin," has been pictured as an engineering sample is probably being evaluated by the company's data-center or cloud customers. The processor has a mammoth core-count of 192-core/384-thread in its high-density cloud-focused variant that uses "Zen 5c" CPU cores. Its regular version that uses larger "Zen 5" cores that can sustain higher clock speeds, also comes with a fairly high core-count of 128-core/256-thread, up from the 96-core/192-thread of the "Zen 4" based EPYC "Genoa."

The EPYC "Turin" server processor based on "Zen 5" comes with an updated sIOD (server I/O die), surrounded by as many as 16 CCDs (CPU complex dies). AMD is expected to build these CCDs on the TSMC N4P foundry node, which is a more advanced version of the TSMC N4 node the company currently uses for its "Phoenix" client processors, and the TSMC N5 node it uses for its "Zen 4" CCD. TSMC claims that the N4P node offers an up to 22% improvement in power efficiency over N5, as well as a 6% increase in transistor density. Each of the "Zen 5" CCDs is confirmed to have 8 CPU cores sharing 32 MB L3 cache memory. A total of 16 such CCDs add up to the processor's 128-core/256-thread number. The high-density "Turin" meant for cloud data-centers, is a whole different beast.

With Windows 11 23H2 setting the stage for increased prevalence of AI in client PC use cases, the new hardware battleground between AMD and its rivals Intel, Apple, and Qualcomm, will be in equipping their mobile processors with sufficient AI acceleration performance. AMD already introduced accelerated AI with the current "Phoenix" processor that debuts Ryzen AI, and its Xilinx XDNA hardware backend that provides a performance of up to 16 TOPS. This will see a 2-3 fold increase with the company's 2024-25 mobile processor lineup, according to a roadmap leak by "Moore's Law is Dead."

At the very top of the pile, in a product segment called "ultimate compute," which consists of large gaming notebooks, mobile workstations, and desktop-replacements; the company's current Ryzen 7045 "Dragon Range" processor will continue throughout 2024. Essentially a non-socketed version of the desktop "Raphael" MCM, "Dragon Range" features up to two 5 nm "Zen 4" CCDs for up to 16 cores, and a 6 nm cIOD. This processor lacks any form of AI acceleration. In 2025, the processor will be succeeded with "Fire Range," a similar non-socketed, mobile-friendly MCM that's derived from "Granite Ridge," with up to two 4 nm "Zen 5" CCDs for up to 16 cores; and the 6 nm cIOD. What's interesting to note here, is that the quasi-roadmap makes no mention of AI acceleration for "Fire Range," which means "Granite Ridge" could miss out on Ryzen AI acceleration from the processor. Modern discrete GPUs from both NVIDIA and AMD support AI accelerators, so this must have been AMD's consideration to exclude an XDNA-based Ryzen AI accelerator on "Fire Range" and "Granite Ridge."

"Strix Point" is the codename for AMD's next-generation mobile processor succeeding the current Ryzen 7040 series "Phoenix." More details of the processor emerged thanks to "All The Watts!!" on Twitter. The CPU of "Strix Point" will be heterogenous, in that it will feature two different kinds of CPU cores, but with essentially the same ISA and IPC. It is rumored that the processor will feature 4 "Zen 5" CPU cores, and 8 "Zen 5c" cores.

Both core types feature an identical IPC, but the "Zen 5" cores can hold onto higher boost frequencies, and have a wider frequency band, than the "Zen 5c" cores. From what we can deduce from the current "Zen 4c" cores, "Zen 5c" cores aren't strictly "efficiency" cores, as they still offer the full breadth of core ISA as "Zen 5," including SMT. In its maximum configuration, "Strix Point" will hence be a 12-core/24-thread processor. The two CPU core types sit in two different CCX (CPU core complexes), the "Zen 5" CCX has 4 cores sharing a 16 MB L3 cache, while the "Zen 5c" CCX shares a 16 MB L3 cache among 8 cores. AMD will probably use a software-based solution to ensure the right kind of workload from the OS is processed by the right kind of CPU core.

A couple of slides from AMD's internal presentation were leaked to the web by Moore's Law is Dead, referencing what's allegedly the next-generation "Zen 5" microarchitecture. Internally, the performance variant of the "Zen 5" core is referred to as "Nirvana," and the CCD chiplet (CPU core die) based on "Nirvana" cores, is codenamed "Eldora." These CCDs will make up either the company's Ryzen "Granite Ridge" desktop processors, or EPYC "Turin" server processors. The cores themselves could also be part of the company's next-generation mobile processors, as part of heterogenous CCXs (CPU core complex), next to "Zen 5c" low-power cores.

In broad strokes, AMD describes "Zen 5" as introducing a 10% to 15% IPC increase over the current "Zen 4." The core will feature a larger 48 KB L1D cache, compared to the current 32 KB. As for the core itself, it features an 8-wide dispatch from the micro-op queue, compared to the 6-wide dispatch of "Zen 4." The integer execution stage gets 6 ALUs, compared to the current 4. The floating point unit gets FP-512 capabilities. Perhaps the biggest announcement is that AMD has increased the maximum cores per CCX from 8 to 16. At this point we don't know if it means that "Eldora" CCD will have 16 cores, or whether it means that the cloud-specific CCD with 16 "Zen 5c" cores will have 16 cores within a single CCX, rather than spread across two CCXs with smaller L3 caches. AMD is leveraging the TSMC 4 nm EUV node for "Eldora," the mobile processor based on "Zen 5" could be based on the more advanced TSMC 3 nm EUV node.

Beating previous reports that AMD is increasing the CPU core count of its mobile monolithic processors from the present 8-core/16-thread to 12-core/24-thread; we are learning that the next-gen processor from the company, codenamed "Strix Point," will in fact be the company's first hybrid processor. The chip is expected to feature two kinds of CPU cores, with "Zen 5" being the microarchitecture behind the performance cores, and "Zen 5c" behind the efficiency cores. An engineering sample featuring 4 P-cores, and 8 E-cores, surfaced on the web, thanks to Performancedatabases. A HWiNFO screenshot reveals the engineering sample's core-configuration of 4x P-cores and 8x E-cores, with identical L1 cache sizes. Things get a little fuzzy with the L2 cache size detection, and L3 cache.

We know from the current "Zen 4c" core design that it is essentially a compacted version of "Zen 4" designed for higher-density chiplets that have 16 cores; and that it has both the same ISA and IPC as "Zen 4," with the only difference being that "Zen 4c" is designed with lower amounts of shared L3 caches at their disposal, are generally configured with lower clock speeds, and have higher energy efficiency than "Zen 4." "Zen 4c" cores also 35% smaller in die-area than "Zen 4." The company could develop "Zen 5c" CPU cores with similar design goals.