Today, IBM revealed IBM Power11, the next generation of IBM Power servers. Redesigned with innovations across its processor, hardware architecture, and virtualization software stack, Power11 is designed to deliver the availability, resiliency, performance, and scalability enterprises demand, for seamless hybrid deployment on-premises or in IBM Cloud.

Organizations across industries have long run their most mission-critical, data-intensive workloads on IBM Power, most notably those within the banking, healthcare, retail, and government spaces. Now, enterprises face an onslaught of new technologies and solutions as they transition into the age of AI. IDC found that one billion new logical applications are expected by 2028, and the proliferation of these systems poses new complexities for companies. IBM built Power11 to deliver simplified, always-on operations with hybrid cloud flexibility for enterprises to maintain competitiveness in the AI era.

To expand its growing influence in the data center market, NVIDIA recently launched the NVLink Fusion program. This initiative enables select partners to integrate their custom-designed chips into the NVIDIA system framework. For example, a partner can connect its custom CPU to an NVIDIA GPU using the 900 GB/s NVLink-C2C interface. However, this collaboration comes with significant restrictions. Any custom chip must be connected to an NVIDIA product, and the company maintains firm control over the critical software that manages these connections. This means partners cannot create truly independent, mix-and-match systems. NVIDIA retains control over the essential communication controller and PHY layers in the NVLink Fusion, which initializes and manages these links. It also mandates a license for third-party hardware to use its NVLink Switch chips.

In response, a growing coalition of tech giants, including AMD, Google, and Intel, is championing an open-standard alternative. Their UALink Consortium released its 1.0 specification in April 2025, defining a public standard for linking up to 1,024 accelerators from any vendor. While NVIDIA currently offers superior raw bandwidth, UALink represents a move toward greater flexibility and cost efficiency. According to reports, eight companies expressed interest in NVLink Fusion. However, the frustration of working with a communication link with limited visibility results in designs that are not always optimal and efficient. NVIDIA sets these standards from the beginning, so any company willing to work with NVLink Fusion is aware of these limitations from the outset. Cloud hyperscalers, such as AWS, GCP, and Azure, have expressed interest among the reported eight customers, so they might swallow this pill and continue working with NVIDIA to gain access to the IP despite the limited information available.

AMD delivered its comprehensive, end-to-end integrated AI platform vision and introduced its open, scalable rack-scale AI infrastructure built on industry standards at its 2025 Advancing AI event.

AMD and its partners showcased:

• How they are building the open AI ecosystem with the new AMD Instinct MI350 Series accelerators
• The continued growth of the AMD ROCm ecosystem
• The company's powerful, new, open rack-scale designs and roadmap that bring leadership rack-scale AI performance beyond 2027

The Ultra Ethernet Consortium (UEC) today announces the release of UEC Specification 1.0, a comprehensive, Ethernet-based communication stack engineered to meet the demanding needs of modern Artificial Intelligence (AI) and High-Performance Computing (HPC) workloads. This release marks a critical step forward in redefining Ethernet for next-generation, data-intensive infrastructure.

UEC Specification 1.0 delivers a high-performance, scalable, and interoperable solution across all layers of the networking stack—including NICs, switches, optics, and cables—enabling seamless multivendor integration and accelerating innovation throughout the ecosystem.

Broadcom Inc. announced today that it is now shipping the Tomahawk 6 switch series, delivering the world's first 102.4 Terabits/sec of switching capacity in a single chip - double the bandwidth of any Ethernet switch currently available on the market. With unprecedented scale, energy efficiency, and AI-optimized features, Tomahawk 6 is built to power the next generation of scale-up and scale-out AI networks, delivering unmatched flexibility with support for 100G/200G SerDes and co-packaged optics (CPO). It offers the industry's most comprehensive set of AI routing features and interconnect options, designed to meet the demands of AI clusters with more than one million XPUs.

"Tomahawk 6 is not just an upgrade - it's a breakthrough," said Ram Velaga, senior vice president and general manager, Core Switching Group, Broadcom. "It marks a turning point in AI infrastructure design, combining the highest bandwidth, power efficiency, and adaptive routing features for scale-up and scale-out networks into one platform. Demand from customers and partners has been unprecedented. Tomahawk 6 is poised to make a rapid and dramatic impact on the deployment of large AI clusters."

Infineon Technologies AG is revolutionizing the power delivery architecture required for future AI data centers. In collaboration with NVIDIA, Infineon is developing the next generation of power systems based on a new architecture with central power generation of 800 V high-voltage direct current (HVDC). The new system architecture significantly increases energy-efficient power distribution across the data center and allows power conversion directly at the AI chip (Graphic Processing Unit, GPU) within the server board. Infineon's expertise in power conversion solutions from grid to core based on all relevant semiconductor materials silicon (Si), silicon carbide (SiC) and gallium nitride (GaN) is accelerating the roadmap to a full scale HVDC architecture.

This revolutionary step paves the way for the implementation of advanced power delivery architectures in accelerated computing data centers and will further enhance reliability and efficiency. As AI data centers already are going beyond 100,000 individual GPUs, the need for more efficient power delivery is becoming increasingly important. AI data centers will require power outputs of one megawatt (MW) and more per IT rack before the end of the decade. Therefore, the HVDC architecture coupled with high-density multiphase solutions will set a new standard for the industry, driving the development of high-quality components and power distribution systems.

Marvell Technology, Inc., a leader in data infrastructure semiconductor solutions, today announced it is teaming with NVIDIA to offer NVLink Fusion technology to customers employing Marvell custom cloud platform silicon. NVLink Fusion is an innovative new offering from NVIDIA for integrating custom XPU silicon with NVIDIA NVLink connectivity, rack-scale hardware architecture, software and other technology, providing customers with greater flexibility and choice in developing next-generation AI infrastructure.

The Marvell custom platform strategy seeks to deliver breakthrough results through unique semiconductor designs and innovative approaches. By combining expertise in system and semiconductor design, advanced process manufacturing, and a comprehensive portfolio of semiconductor platform solutions and IP—including electrical and optical serializer/deserializers (SerDes), die-to-die interconnects for 2D and 3D devices, advanced packaging, silicon photonics, co-packaged copper, custom high-bandwidth memory (HBM), system-on-chip (SoC) fabrics, optical IO, and compute fabric interfaces such as PCIe Gen 7—Marvell is able to create platforms in collaboration with customers that transform infrastructure performance, efficiency and value.

AMD has announced a definitive agreement to sell ZT Systems' data center infrastructure manufacturing business to Sanmina for $3 billion in cash and stock, which includes a contingent payment of up to $450 million. This announcement follows earlier reports from April that AMD was looking to divest the facility it had acquired as part of its $4.9 billion purchase of ZT in March 2025. The deal set to wrap up around late 2025 shows AMD's plan to steer clear of making products that compete with its customers. At the same time, AMD will keep ZT Systems' design and customer support teams to speed up the rollout of AMD AI systems for cloud clients. Sanmina will also become a top choice for introducing new products in AMD's cloud rack and large-scale AI solutions. "By combining the deep experience of our AI systems design team with our new preferred NPI partnership with Sanmina, we expect to strengthen our U.S-based manufacturing capabilities for rack and cluster-scale AI systems and accelerate quality and time-to-market for our cloud customers," said Forrest Norrod, executive vice president and general manager, Data Center Solutions business unit at AMD.

The sale drew a lot of interest from different manufacturers, with early reports showing that Taiwanese OEM makers Compal and Wiwynn were the top choices, along with U.S. electronics firm Jabil. Inventec and Pegatron decided not to take part. Sanmina, the final buyer, is a U.S.-based company that provides integrated manufacturing solutions to the global Electronic Manufacturing Services field. Jure Sola, Chairman and CEO of Sanmina Corporation, said that ZT Systems' skills in liquid cooling, its manufacturing ability, and its know-how in cloud and AI setup will add to Sanmina's worldwide range and vertical integration skills. "Together, we will be better able to deliver a competitive advantage to our customers with solutions for the entire product lifecycle. We look forward to our ongoing partnership with AMD as we work together to set the standard for quality and flexibility to benefit the entire AI ecosystem." said Jure Sola, Chairman and CEO of Sanmina Corporation.

AMD today announced financial results for the first quarter of 2025. First quarter revenue was $7.4 billion, gross margin was 50%, operating income was $806 million, net income was $709 million and diluted earnings per share was $0.44. On a non-GAAP(*) basis, gross margin was 54%, operating income was $1.8 billion, net income was $1.6 billion and diluted earnings per share was $0.96.

"We delivered an outstanding start to 2025 as year-over-year growth accelerated for the fourth consecutive quarter driven by strength in our core businesses and expanding data center and AI momentum," said Dr. Lisa Su, AMD chair and CEO. "Despite the dynamic macro and regulatory environment, our first quarter results and second quarter outlook highlight the strength of our differentiated product portfolio and consistent execution positioning us well for strong growth in 2025."

Astera Labs, Inc., a global leader in semiconductor-based connectivity solutions for AI and cloud infrastructure, today announced its purpose-built PCIe 6 connectivity portfolio is ramping production to fast-track deployments of modern AI platforms at scale. Now featuring gearbox connectivity solutions alongside fabric switches, retimers, and active cable modules, Astera Labs' expanding PCIe 6 portfolio provides a comprehensive connectivity platform to deliver unparalleled performance, utilization, and scalability for next-generation AI and general-compute systems. Along with Astera Labs' demonstrated PCIe 6 connectivity over optical media, the portfolio will provide even greater AI rack-scale distance optionality. The transition to PCIe 6 is fueled by the insatiable demand for higher compute, memory, networking, and storage data throughput, ensuring advanced AI accelerators and GPUs operate at peak efficiency.

Thad Omura, Chief Business Officer, said, "Our PCIe 6 solutions have successfully completed qualification with leading AI and cloud server customers, and we are ramping up to volume production in parallel with their next generation AI platform rollouts. By continuing to expand our industry-leading PCIe connectivity portfolio with additional innovative solutions that includes Scorpio Fabric Switches, Aries Retimers, Gearboxes, Smart Cable Modules, and PCIe over optics technology, we are providing our hyperscaler and data center partners all the necessary tools to accelerate the development and deployment of leading-edge AI platforms."

Marvell Technology, Inc., a leader in data infrastructure semiconductor solutions, today announced in collaboration with TeraHop, a global optical solutions provider for AI driven data centers, the demonstration of the industry's first end-to-end PCIe Gen 6 over optics in the Marvell booth #2129 at OFC 2025. The demonstration will showcase the extension of PCIe reach beyond traditional electrical limits to enable low-latency, standards-based AI scale-up infrastructure.

As AI workloads drive exponential data growth, PCIe connectivity must evolve to support higher bandwidth and longer reach. The Marvell Alaska P PCIe Gen 6 retimer and its PCIe Gen 7 SerDes technology enable low-latency, low bit-error-rate transmission over optical fiber, delivering the scalability, power efficiency, and high performance required for next-generation accelerated infrastructure. With PCIe over optics, system designers will be able to take advantage of longer links between devices that feature the low latency of PCIe technology.

According to the International Data Corporation (IDC) Worldwide Quarterly Server Tracker, the server market reached a record $77.3 billion dollars in revenue during the last quarter of the year. This quarter showed the second highest growth rate since 2019 with a year-over-year increase of 91% in vendor revenue. Revenue generated from x86 servers increased 59.9% in 2024Q4 to $54.8 billion while Non-x86 servers increased 262.1% year over year to $22.5 billion.

Revenue for servers with an embedded GPU in the fourth quarter of 2024 grew 192.6% year-over-year and for the full year 2024, more than half of the server market revenue came from servers with an embedded GPU. NVIDIA continues dominating the server GPU space with over 90% of the total shipments with and embedded GPU in 2024Q4. The fast pace at which hyperscalers and cloud service providers have been adopting servers with embedded GPUs has fueled the server market growth which has more than doubled in size since 2020 with revenue of $235.7 billion dollars for the full year 2024.

MSI, a leading global provider of high-performance server solutions, unveiled its next-generation server platforms—ORv3 Servers, DC-MHS Servers, and NVIDIA MGX AI Servers—at CloudFest 2025, held from March 18-20 at booth H02. The ORv3 Servers focus on modularity and standardization to enable seamless integration and rapid scalability for hyperscale growth. Complementing this, the DC-MHS Servers emphasize modular flexibility, allowing quick reconfiguration to adapt to diverse data center requirements while maximizing rack density for sustainable operations. Together with NVIDIA MGX AI Servers, which deliver exceptional performance for AI and HPC workloads, MSI's comprehensive solutions empower enterprises and hyperscalers to redefine cloud infrastructure with unmatched flexibility and performance.

"We're excited to present MSI's vision for the future of cloud infrastructure." said Danny Hsu, General Manager of MSI's Enterprise Platform Solutions. "Our next-generation server platforms address the critical needs of scalability, efficiency, and sustainability. By offering modular flexibility, seamless integration, and exceptional performance, we empower businesses, hyperscalers, and enterprise data centers to innovate, scale, and lead in this cloud-powered era."

IBM (NYSE: IBM) today announced it has completed its acquisition of HashiCorp, whose products automate and secure the infrastructure that underpins hybrid cloud applications and generative AI. Together the companies' capabilities will help clients accelerate innovation, strengthen security, and get more value from the cloud.

Today nearly 75% of enterprises are using hybrid cloud, including public clouds from hyperscalers and on-prem data centers, which can enable true innovation with a consistent approach to delivering and managing that infrastructure at scale. Enterprises are looking for ways to more efficiently manage and modernize cloud infrastructure and security tasks from initial planning and design, to ongoing maintenance. By 2028, it is projected that generative AI will lead to the creation of 1 billion new cloud-native applications. Supporting this scale requires infrastructure automation far beyond the capacity of the workforce alone.

STMicroelectronics, a global semiconductor leader serving customers across the spectrum of electronics applications, is unveiling its next generation of proprietary technologies for higher-performing optical interconnect in datacenters and AI clusters. With the exponential growth of AI computing needs, challenges arise in performance and energy efficiency across computing, memory, power supply, and the interconnections linking them. ST is helping hyperscalers, and the leading optical module provider, overcome those challenges with new silicon photonics and next-gen BiCMOS technologies, scheduled to ramp up from the second half of 2025 for 800 Gb/s and 1.6 Tb/s optical modules.

At the heart of interconnections in a datacenter are thousands, or even hundreds of thousands, of optical transceivers. These devices convert optical into electrical signals and vice versa to allow data flow between graphics processing unit (GPU) computing resources, switches and storage. Inside these transceivers, ST's new, proprietary silicon photonics (SiPho) technology will bring customers the ability to integrate multiple complex components into one single chip, while ST's next-gen, proprietary BiCMOS technology brings ultra high-speed and low power optical connectivity, which are key to sustain the AI growth.

Numem, an innovator focused on accelerating memory for AI workloads, will be at the upcoming Chiplet Summit to showcase its high-performance solutions. By accelerating the delivery of data via new memory subsystem designs, Numem solutions are re-architecting the hierarchy of AI memory tiers to eliminate the bottlenecks that negatively impact power and performance.

The rapid growth of AI workloads and AI Processor/GPUs are exacerbating the memory bottleneck caused by the slowing performance improvements and scalability of SRAM and DRAM - presenting a major obstacle to maximizing system performance. To overcome this, there is a pressing need for intelligent memory solutions that offer higher power efficiency and greater bandwidth, coupled with a reevaluation of traditional memory architectures.

Alphawave Semi (LSE: AWE), a global leader in high-speed connectivity and compute silicon for the world's technology infrastructure, proudly introduces the industry's first 64 Gbps Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) IP Subsystem to deliver unprecedented chiplet interconnect data rates, setting a new standard for ultra-high-performance D2D connectivity solutions in the industry. The third generation, 64 Gbps IP Subsystem builds on the successes of the most recent Gen 2 36 Gbps IP subsystem and silicon-proven Gen 1 24 Gbps and is available in TSMC's 3 nm Technology for both Standard and Advanced packaging. The silicon proven success and tapeout milestones pave the way for Alphawave Semi's Gen 3 UCIe IP subsystem offering.

Alphawave Semi is set to revolutionize connectivity with its Gen 3 64 Gbps UCIe IP, delivering a bandwidth density of over 20 Tbps/mm, with ultra-low power and latency. This solution is highly configurable supporting multiple protocols, including AXI-4, AXI-S, CXS, CHI and CHI-C2C to address the growing demands for high-performance connectivity across disaggregated systems in High-Performance Computing (HPC), Data Centers, and Artificial Intelligence (AI) applications.

Marvell Technology, Inc. (NASDAQ: MRVL), a leader in data infrastructure semiconductor solutions, today announced that it has pioneered a new custom HBM compute architecture that enables XPUs to achieve greater compute and memory density. The new technology is available to all of its custom silicon customers to improve the performance, efficiency and TCO of their custom XPUs. Marvell is collaborating with its cloud customers and leading HBM manufacturers, Micron, Samsung Electronics, and SK hynix to define and develop custom HBM solutions for next-generation XPUs.

HBM is a critical component integrated within the XPU using advanced 2.5D packaging technology and high-speed industry-standard interfaces. However, the scaling of XPUs is limited by the current standard interface-based architecture. The new Marvell custom HBM compute architecture introduces tailored interfaces to optimize performance, power, die size, and cost for specific XPU designs. This approach considers the compute silicon, HBM stacks, and packaging. By customizing the HBM memory subsystem, including the stack itself, Marvell is advancing customization in cloud data center infrastructure. Marvell is collaborating with major HBM makers to implement this new architecture and meet cloud data center operators' needs.

Synopsys, Inc. today announced the industry's first Ultra Ethernet IP and UALink IP solutions, including controllers, PHYs, and verification IP, to meet the demand for standards-based, high-bandwidth, and low-latency HPC and AI accelerator interconnects. As hyperscale data center infrastructures evolve to support the processing of trillions of parameters in large language models, they must scale to hundreds of thousands of accelerators with highly efficient and fast connections. Synopsys Ultra Ethernet and UALink IP will provide a holistic, low-risk solution for high-speed and low-latency communication to scale-up and scale-out AI architectures.

"For more than 25 years, Synopsys has been at the forefront of providing best-in-class IP solutions that enable designers to accelerate the integration of standards-based functionality," said Neeraj Paliwal, senior vice president of IP product management at Synopsys. "With the industry's first Ultra Ethernet and UALink IP, companies can get a head start on developing a new generation of high-performance chips and systems with broad interoperability to scale future AI and HPC infrastructure."

AMD has unveiled its latest EPYC processors, codenamed "Turin," featuring Zen 5 and Zen 5C dense cores. Phoronix's thorough testing reveals remarkable advancements in performance, efficiency, and value. The new lineup includes the EPYC 9575F (64-core), EPYC 9755 (128-core), and EPYC 9965 (192-core) models, all showing impressive capabilities across various server and HPC workloads. In benchmarks, a dual-socket configuration of the 128-core EPYC 9755 Turin outperformed Intel's dual Xeon "Granite Rapids" 6980P setup with MRDIMM-8800 by 40% in the geometric mean of all tests. Surprisingly, even a single EPYC 9755 or EPYC 9965 matched the dual Xeon 6980P in expanded tests with regular DDR5-6400. Within AMD's lineup, the EPYC 9755 showed a 1.55x performance increase over its predecessor, the 96-core EPYC 9654 "Genoa". The EPYC 9965 surpassed the dual EPYC 9754 "Bergamo" by 45%.

These gains come with improved efficiency. While power consumption increased moderately, performance improvements resulted in better overall efficiency. For example, the EPYC 9965 used 32% more power than the EPYC 9654 but delivered 1.55x the performance. Power consumption remains competitive: the EPYC 9965 averaged 275 Watts (peak 461 Watts), the EPYC 9755 averaged 324 Watts (peak 500 Watts), while Intel's Xeon 6980P averaged 322 Watts (peak 547 Watts). AMD's pricing strategy adds to the appeal. The 192-core model is priced at $14,813, compared to Intel's 128-core CPU at $17,800. This competitive pricing, combined with superior performance per dollar and watt, has resonated with hyperscalers. Estimates suggest 50-60% of hyperscale deployments now use AMD processors.

Late Tuesday, Microsoft Azure shared an interesting picture on its social media platform X, showcasing the pinnacle of GPU-accelerated servers—NVIDIA "Blackwell" GB200-powered AI systems. Microsoft is one of NVIDIA's largest customers, and the company often receives products first to integrate into its cloud and company infrastructure. Even NVIDIA listens to feedback from companies like Microsoft about designing future products, especially those like the now-canceled NVL36x2 system. The picture below shows a massive cluster that roughly divides the compute area into a single-third of the entire system, with a gigantic two-thirds of the system dedicated to closed-loop liquid cooling.

The entire system is connected using Infiniband networking, a standard for GPU-accelerated systems due to its lower latency in packet transfer. While the details of the system are scarce, we can see that the integrated closed-loop liquid cooling allows the GPU racks to be in a 1U form for increased density. Given that these systems will go into the wider Microsoft Azure data centers, a system needs to be easily maintained and cooled. There are indeed limits in power and heat output that Microsoft's data centers can handle, so these types of systems often fit inside internal specifications that Microsoft designs. There are more compute-dense systems, of course, like NVIDIA's NVL72, but hyperscalers should usually opt for other custom solutions that fit into their data center specifications. Finally, Microsoft noted that we can expect to see more details at the upcoming Microsoft Ignite conference in November and learn more about its GB200-powered AI systems.

Oracle today announced the first zettascale cloud computing clusters accelerated by the NVIDIA Blackwell platform. Oracle Cloud Infrastructure (OCI) is now taking orders for the largest AI supercomputer in the cloud—available with up to 131,072 NVIDIA Blackwell GPUs.

"We have one of the broadest AI infrastructure offerings and are supporting customers that are running some of the most demanding AI workloads in the cloud," said Mahesh Thiagarajan, executive vice president, Oracle Cloud Infrastructure. "With Oracle's distributed cloud, customers have the flexibility to deploy cloud and AI services wherever they choose while preserving the highest levels of data and AI sovereignty."

Intel's 5th generation Xeon Scalable processors codenamed Emerald Rapids, have been shipping since late 2023 and are installed at numerous servers today. However, Emerald Rapids appears to possess more performance and efficiency tricks than it initially revealed at launch. According to the report from Phoronix, reporting on a Linux kernel patch sent to the Linux Kernel Mailing List (LKML), there is a chance for up to 38% performance increase while using up to 18% less power on all Intel 5th generation Xeon machines. Thanks to Canonical (maker of Ubuntu Linux) engineer Pedro Henrique Kopper, who explained the patch on the LKML, we found out that changing a single line of code yielded this massive increase.

Ubuntu Linux, as well as many other distributions, ship with Energy Performance Preference (EPP) for Emerald Rapids with a "balance_performance" value of 128. However, changing the value to 32 now yields a massive performance improvement alongside using less power. The EPP "balance_performance" is the default out-of-the-box setting for many Linux distributions. Users manually setting the "performance" mode in the EPP are not expecting any increase from this patch, as the "balance_performance" mode had issues balancing power and efficiency. Introducing this new setting yields more performance for machines that run at default settings, and this is especially important for data centers where the need for lower power and increased performance is constantly surging. Especially at hyperscalers like Amazon, Google, and Meta, which may run tens of thousands of these CPUs at default settings to keep them stable and well-cooled, who can now enjoy a massive performance increase with less power consumed.Below, you can see the patch quote as well as more performance/power measurements.

Alphawave Semi, a global leader in high-speed connectivity and compute silicon for the world's technology infrastructure, has launched the industry's first 3 nm successful silicon bring-up of Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) IP with TSMC's Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging technology.

The complete PHY and Controller subsystem was developed in collaboration with TSMC and targets applications such as hyperscaler, high-performance computing (HPC) and artificial intelligence (AI).

While we are all used to having a system with a CPU, GPU, and, recently, NPU—X-Silicon Inc. (XSi), a startup founded by former Silicon Valley veterans—has unveiled an interesting RISC-V processor that can simultaneously handle CPU, GPU, and NPU workloads in a chip. This innovative chip architecture, which will be open-source, aims to provide a flexible and efficient solution for a wide range of applications, including artificial intelligence, virtual reality, automotive systems, and IoT devices. The new microprocessor combines a RISC-V CPU core with vector capabilities and GPU acceleration into a single chip, creating a versatile all-in-one processor. By integrating the functionality of a CPU and GPU into a single core, X-Silicon's design offers several advantages over traditional architectures. The chip utilizes the open-source RISC-V instruction set architecture (ISA) for both CPU and GPU operations, running a single instruction stream. This approach promises lower memory footprint execution and improved efficiency, as there is no need to copy data between separate CPU and GPU memory spaces.

Called the C-GPU architecture, X-Silicon uses RISC-V Vector Core, which has 16 32-bit FPUs and a Scaler ALU for processing regular integers as well as floating point instructions. A unified instruction decoder feeds the cores, which are connected to a thread scheduler, texture unit, rasterizer, clipping engine, neural engine, and pixel processors. All is fed into a frame buffer, which feeds the video engine for video output. The setup of the cores allows the users to program each core individually for HPC, AI, video, or graphics workloads. Without software, there is no usable chip, which prompts X-Silicon to work on OpenGL ES, Vulkan, Mesa, and OpenCL APIs. Additionally, the company plans to release a hardware abstraction layer (HAL) for direct chip programming. According to Jon Peddie Research (JPR), the industry has been seeking an open-standard GPU that is flexible and scalable enough to support various markets. X-Silicon's CPU/GPU hybrid chip aims to address this need by providing manufacturers with a single, open-chip design that can handle any desired workload. The XSi gave no timeline, but it has plans to distribute the IP to OEMs and hyperscalers, so the first silicon is still away.