1P and 2P System Architecture

As we briefly examined on page 1, AMD is trying their hardest to convince you that their 2P and 1P socket systems are inherently better than the competition. Intel's Broadwell-E/EP platform requires a 2P system to avail the maximum possible I/O in terms of PCIe lanes, system memory, and the presence of a dedicated CPU-to-CPU link that can not be used for any other I/O operation. As such, customers may have hardware and monetary investments in the form of PCIe switches and an external PCH in order to get more I/O devices connected. PCIe switches also have limited upstream aggregated bandwidth, which further complicates things. This is a clever way of saying that the EPYC 2P system offers more - more PCIe lanes, more system memory slots, the Infinity Fabric connection links, and an integrated SCH. In fact, the 1P system offers just as much with up to a 32C/64T CPU having the same 16 DDR4 memory slots and 128 PCIe lanes, which minimizes the need for PCIe switches.

EPYC Power Efficiency

If there is one thing common to server platforms, it is that the CPUs remain the components that consume the majority of electrical power. AMD estimates the CPUs in your average 2P system to consume more than the rest of the components put together, and thus, it is logical to have optimal performance-to-power balance here. In order to do so, AMD has integrated thousands of sensors on each CCX as well as the entire SoC, such that a system's management unit, in conjunction with Infinity Fabric, will automatically identify the optimal operating point. This is done by having the system scan all cores, up to 32, as many as 1000 times per second to identify any change from the optimal operating point.

Power consumption and temperature monitoring enables automatic changes to the CPU frequency to cater to thermal limits, as seen above. This also accounts for real-time changes to workload such that CPU activity is also accounted for before adjusting the CPU frequency. The optimal operating point is determined by all these factors together, and the CPU core voltage is adjusted accordingly such that one of several fine-grained P-states are the next chosen operating point.


EPYC also provides more control to the user when it comes to choosing between a performance-determined and power-determined operation. AMD recognizes that different users have different preferences here, and also that the silicon in the CPU can have an impact on power draw as a result of slow-high and/or fast-low leakage parts. This is where configurable power limits come in, which in some cases allows users to adopt specific performance/power boot-time configurations within a range of +/- 15 W.