Conclusion

This article offers a brief exploration of DRAM temperatures and the factors that contribute to unstable memory and system crashes when adjusting timings for system maximum performance gains. Along the way, some intriguing findings emerged that will undoubtedly help enthusiasts avoid common pitfalls when fine-tuning their memory. In summary, a few key points can be confirmed: both DRAM frequency and voltage independently contribute to temperature increases. Additionally, CAS value is influenced by both voltage and DRAM temperature. Finally, the maximum tREFi value for SK Hynix A-Die is strictly constrained by temperature.

The testing for this article was prompted from a forum question asking why DRAM temperature testing was removed from reviews. The answer is straightforward: the SPD sensor alone cannot be fully trusted at this time without further investigation. This led to further testing without avail and put in question the reliability of the SPD sensor and how best to ensure accurate results. To maintain fairness and accuracy, the DRAM thermal test was temporarily suspended until these results could be confirmed as reliable way to measure the DRAM temperature. The core issue lies in how the SPD reader measures temperature and whether a thermal pad is placed between the PMIC and the heat spreader factor into the reported value. With LN2 heat spreaders, the thermal deviation between the DRAM and SPD sensor is relatively small being only 1-3°C even at 1.5 V with DDR5-8000. This suggests that the SPD PCB sensor and the DRAM maintain similar temperatures due to excellent thermal dissipation of the heat spreaders.

This article marks the first major step toward understanding how temperatures can be a major factor in DRAM tuning. The challenges that memory vendors face when designing a product with XMP and EXPO profiles all the while ensuring product reliability. Unfortunately, the seemingly simple question that started this all remains still left unanswered and has instead raised even more questions about DRAM. For retail memory kits, additional factors such as dual-rank configurations, the type of thermal pads used, and the extent of heat spreader coverage can lead to greater temperature deviations which could introduce more variables and complexity to the overall analysis of what has been covered in this article.

What's Next?

Based on the results of today's test, we invite the TPU community to share their thoughts on what areas should be explored further and which topics from this article could be expanded upon. Your feedback and suggestions will help guide the next steps in this ongoing investigation of DRAM temperature and the variables that go into optimizing system performance.