The Arrow Lake Microarchitecture

Intel developed the Arrow Lake processor microarchitecture to address two of its biggest client processor market segments, the desktop, and conventional notebooks. For ultraportable notebooks without discrete graphics, the company developed a grounds-up new silicon under the Lunar Lake microarchitecture. Lunar Lake shares many IP blocks with Arrow Lake, especially the CPU cores, but there are several differences. Intel uses the form-factor designation "S" to refer to mainstream desktops, and hence the "Arrow Lake-S" silicon powers all five processor SKUs being announced today. The company plans to launch the "Arrow Lake-H" processor for mainstream notebooks, and the "Arrow Lake-HX" processor for enthusiast notebooks, in Q1-2025. There are no processor model announcements for the H and HX variants today.


With "Arrow Lake," Intel retains the disaggregated tile-based processor design that it embarked upon with "Meteor Lake" in the client segment. The governing idea here is that you needn't built a large monolithic chip based on the latest foundry node, but rather identify specific IP blocks that benefit the most from the node, such as the CPU cores and the iGPU, and build just those components on the latest nodes, as breakout tiles. The rest of the processor that deals mainly with platform I/O interfaces, can be built on a tile with a slightly older foundry node, thereby letting Intel maximize its yields on the latest foundry node, since the tiles it builds on these nodes are smaller.


There are five types of tiles making up "Arrow Lake." It begins with the Foveros base tile. This is a silicon interposer that sits on the fiberglass package substrates, and seats the other tiles on top. An interposer facilitates high-density microscopic wiring between tiles or chiplets stacked on top of it, which would otherwise not be achievable on the fiberglass substrate. This is the key difference between Intel's tile-based processor, and AMD's chiplet-based ones, which rely on the package substrate to connect the CPU complex dies (CCDs) to the I/O die (cIOD). The perks of this interposer include closer physical proximity of the tiles, benefitting latency, and lower power needed to move data around between the tiles.

Compute Tile

The first and arguably most important tile is the Compute tile. This is built on the 3 nm TSMC N3B process. This contains the CPU cores. The core-complex consists of eight "Lion Cove" performance cores (P-cores), and sixteen "Skymont" efficiency cores (E-cores). The E-cores are arranged in four clusters of 4 cores, each. The eight P-cores and four E-core clusters are arranged along a ring-bus interconnect, and share a 36 MB last-level L3 cache. A slight change from "Alder Lake" and "Raptor Lake" seen in the Compute tile of "Arrow Lake" is the physical arrangement of the P-cores and E-core clusters. On "Raptor Lake," the eight P-cores are located on one end of the compute complex, and the two or four E-core clusters on the other end. With "Arrow Lake," they are arranged in an alternating fashion as shown in the slide above. Intel says this is to reduce the concentration of heat generated from the P-cores in compute heavy scenarios such as gaming. It also puts every E-core cluster just one ring stop away from a P-core, which should reduce latencies for threads migrating between the P-cores and E-cores.

SoC Tile

The next most important tile is the SoC tile. This takes up a mostly-central region of the chip, and is built on the 6 nm TSMC N6 node. There are no low-power island E-cores on this tile, unlike with "Meteor Lake." The only logic heavy component is the NPU 3. This tile contains the dual-channel DDR5 memory controller, the DDR5 memory PHY, and the processor's PCI-Express root complex.


Not counting the DMI 4.0 x8 chipset bus, the processor puts out 20 PCIe Gen 5 lanes. 16 of these are dedicated to the PEG interface (for discrete graphics), and four to a dedicated CPU-attached M.2 NVMe slot. There are actually two CPU-attached M.2 slots. Besides the Gen 5 x4, there is a second Gen 4 x4 connection from the processor. This one comes from the breakout I/O tile, which also contains an integrated 40 Gbps Thunderbolt 4 controller. The SoC tile also contains three of the iGPU's allied components, the Display Engine, the Media Acceleration engine, and the Display I/O.


The dual-channel DDR5 memory controller of "Arrow Lake-S" supports up to 192 GB of dual-channel memory, with up to 48 GB density per DIMM. It comes with native support for JEDEC DDR5-6400, and Intel says that DDR5-8000 is the "sweetspot" overclocking memory speed. The processors also support overclocked memory speeds well beyond this. There are already announcements of DDR5-9600, and throughout 2025 we should see memory speeds well beyond 10000 MT/s, using memory modules that use CKD chips (CUDIMMs or CSODIMMs). ECC is supported by the architecture, though not on the Z890 chipset, nor by the processor models being announced today.


The SoC tile integrates an NPU 3 unit, which appears to have been carried over from "Meteor Lake." This is based on Intel's 3rd Gen NPU architecture, compared to the 4th Gen NPU on "Lunar Lake." NPU 3 has a peak throughput of 13 AI TOPS, which means it falls short of the 40 TOPS requirement for Microsoft Copilot+ local acceleration. The unit contains two NCEs (neural compute engines), with two INT8/FP16 MAC arrays, four SHAVE DSPs, and a 4 MB scratchpad RAM.

Graphics Tile

The third key tile of "Arrow Lake" is the Graphics tile, built on the Xe-LPG graphics architecture, which, interestingly, is a generation older than the Xe2 architecture powering the iGPU of "Lunar Lake." The Graphics tile is built on the 5 nm TSMC N5P node. The Graphics tile only contains the iGPU's number crunching and graphics rendering machinery, in the form of a single Xe Rendering Slice with four Xe cores, worth 64 execution units (EUs) or 512 unified shaders. The Xe cores of Arrow Lake's graphics tile lack XMX units. Any AI acceleration is in the form of DP4a, and not XMX. The enthusiast mobile "Arrow Lake-HX" uses the same Graphics tile. On the other hand, the "Arrow Lake-H" comes with a larger Graphics tile with eight Xe cores (128 EU, 1,024 unified shaders), and the Xe cores there feature XMX units. Despite having just 4 Xe cores, the Graphics tiles of "Arrow Lake-S" and "Arrow Lake-HX" feature ray tracing units, one per Xe core, which give them full DirectX 12 Ultimate capability. Intel has also given the iGPU a rather large 4 MB L2 cache, which cushions transfers between it and the SoC tile.


The Media Engine of "Arrow Lake-S" provides hardware-acceleration for video of up to 8K @ 60 Hz with 10-bit HDR, with supported formats that include VP9, AVC, HEVC, AV1, and SSC. Hardware-accelerated encoding is supported for resolutions of up to 8K @ 120 Hz with 10-bit HDR, with supported formats that include VP9, AVC, HEVC, and AV1. The Display Engine supports up to four display pipes with four low-power pipes, and support for up to 5 display ports. Standards supported include HDMI 2.1, DisplayPort 2.1, and eDP 1.4. Resolutions supported include 8K @ 60 Hz HDR, or four 4K @ 60 Hz HDR, or 1080p @ 360 Hz, or 1440p @ 360 Hz.