The Meteor Lake Philosophy

Intel "Meteor Lake" is the company's first consumer disaggregated processor architecture, which is not exactly an antithesis of the aggregation effort Intel undertook over the past two decades. Beginning with 2003, Intel aggregated 2P (multiprocessor) into a single package to develop multi-core processors. In 2007, it aggregated a big portion of the northbridge (aka core-logic) into the package, bringing the memory controller next to the CPU cores for superior latencies and performance, than having them on a discrete northbridge. The next step for aggregation was bringing the integrated graphics (iGPU) into the package, where it could have low-latency access to the memory controller, since graphics is a memory-sensitive device. This was done in two steps. "Clarkdale" briefly put the iGPU and memory controller into a separate 45 nm die from the 32 nm CPU complex die; and with the 2011 "Sandy Bridge," the iGPU and memory controllers were fully merged into a monolithic 32 nm silicon alongside the CPU cores.


This would go on to become the basic construct of Intel client processors for the next 12 years, right up to the current "Raptor Lake." 2023 is a different world. Intel's foundry technology leadership is lost to TSMC, there is tremendous demand for the latest foundry nodes to build chips that pretty much power our modern civilization, and although Intel has been able to keep its new Intel 4 node on track, the company cannot hope to build large monolithic processors on the node anymore. This calls for Intel to disaggregate the processor, not back into discrete devices scattered across the motherboard, but something else.

The Need to Disaggregate and How to Go About it

A disaggregated processor is not a multi-chip module (MCM) in the strictest sense of the term. In an MCM, you are bringing independent devices that can otherwise exist on their own packages, together on a single substrate. An example of an MCM would be the mobile Intel Core package that combines the processor die and PCH die on a single package. Here, the PCH can exist as a discrete device like it does on desktop motherboards, without any performance loss. In a disaggregated processor (or chiplet device), the individual devices residing on separate chiplets are located not just on the same package (like in an MCM), but in extremely close vicinity to each other, with high performance interconnects running between them. These chiplets cannot exist on separate packages, because then there would be prohibitive amounts of latency introduced, and the processor cannot attain its desired performance—it cannot be a sum of its parts.

AMD has been disaggregating its processors since Ryzen 3000 "Zen 2," where the CPU cores had been spun off into separate 7 nm chiplets talking to a 12 nm I/O die that contained the rest of the processor with memory controllers, PCIe interface, and an integrated SoC. It would have cost AMD a lot more to build a monolithic 16-core processor on 7 nm at the time, compared to this approach. AMD discovered that the components on the 12 nm die didn't really benefit much from the switch to 7 nm to warrant building a monolithic die. The resulting consumer processor would use up to two 8-core CPU complex dies, each barely the size of a fingernail, but place up to eight of these on the larger EPYC server processors, minimizing R&D costs.


Intel's approach to the disaggregated processor is a lot more complex, and is driven by the fact that "Meteor Lake" has three distinct logic devices—the CPU, the iGPU, and the NPU (neural processing unit). Each of these is a bandwidth hungry device that sits on a separate die, and we'll try to explain the need to arrange them the way they are.


The "Meteor Lake" Processor is a collection of four distinct tiles (chiplets), and an base tile that serves as an intelligent interposer, facilitating high-density, low-latency wiring between them. The four tiles are Compute, Graphics, SoC, and I/O.


The Compute tile contains the processor's CPU cores, or its main compute machinery. The SoC tile contains the all important NPU (neural processing unit) that forms the hardware backend of Intel AI Boost, besides the processor's media accelerator and display controller. It also contains the processor's memory controllers and PCI-Express root complex. Besides these, the SoC tile has a surprise component called the Island E-cores (a lot more on this fascinating component later). The Graphics tile, as its name suggests, contains the iGPU, specifically the graphics rendering and graphics compute machinery, but minus the display and media accelerators. The I/O tile, although physically separate from the SoC tile, is an extension of it, and contains all the physical layer interfaces of the processor.

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