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Upcoming Hardware Launches 2024 (Updated Nov 2024)
(414 Comments) »Introduction
In this article, which our team will regularly update, we will maintain a growing list of information pertaining to upcoming hardware releases based on leaks and official announcements as we spot them. There will obviously be a ton of rumors on unreleased hardware, and it is our goal to—based on our years of industry experience—exclude the crazy ones. In addition to these upcoming hardware release news, we will regularly adjust the structure of this article to better organize information. Each time an important change is made to this article, it will re-appear on our front page with a "new" banner, and the additions will be documented in the forum comments thread. This article will not leak information we signed an NDA for.Feel free to share your opinions and tips in the forum comments thread and subscribe to the same thread for updates.
Last Update (Nov 7th):
- Updated AMD Zen 5 Mobile
- Updated AMD Zen 5 Threadripper / Threadripper 9000
- Updated AMD Ryzen 5000 XT
- Added AMD Ryzen 9000 X3D Series
- Added AMD Ryzen Z2 Extreme
- Added Intel Arrow Lake "KS"
- Added Intel Arrow Lake Mobile
- Updated Intel Arrow Lake Refresh
- Updated Intel Panther Lake
- Updated Intel Clearwater Forest
- Updated Intel Nova Lake
- Added Intel Beast Lake
- Updated NVIDIA Arm CPUs for Desktop
- Updated NVIDIA Blackwell / GeForce RTX 50
- Added AMD Radeon RX 7300 and 7400
- Added AMD Radeon RX 7650 GRE
- Updated AMD RDNA 4 / Radeon RX 8000 Series
- Added AMD UDNA
- Updated Intel Battlemage Architecture
- Updated AMD B850 / B450 Chipsets
- Updated Intel 800-Series Chipsets
- Updated GDDR7 Graphics Memory
- Updated HBM3e Memory
- Updated HBM4 Memory
- Added HBM-PIM Memory
- Added HBM5 Memory
- Updated Samsung 2 nanometer
- Updated Samsung 1.4 nanometer
- Updated Intel 20A
- Updated Intel 18A
- Updated Hynix 400-layer 3D NAND Flash
- Updated Samsung 430-layer 3D NAND Flash
- Updated Samsung 1000-layer 3D NAND Flash
- Removed launched products: AMD Ryzen 5000 XT, Zen 5 / Ryzen 9000, Intel Arrow Lake, Intel Lunar Lake, Intel Granite Rapids, Intel Sierra Forest, AMD CDNA3, X690E, X870E, X870, Intel Z890, Micron 232-layer QLC, Hynix 238-layer TLC, Intel 3 process
Processors
AMD Zen 5 Mobile [updated]
- Release Date: Q1 2025 # #
- Goes up against Intel Lunar Lake #
- 8c/16t, with 4 Zen 5 cores and 4 Zen 5c cores #
- Clocks around 4 GHz #
- 256-bit LPDDR5X memory support # #
- Up to 40 RDNA 3.5 compute units (2560 cores) #
- XDNA 2 AI Engine #
- FP8 platform (15 - 45 W) #
AMD Zen 5 Threadripper / Threadripper 9000 [updated]
- Release Date: 2025 #
- Codename: Shimada Peak #
- Zen 5 architecture #
- Same socket as Zen 4 Threadripper #
- 96 Cores #
- Threadripper gets support for 3D V-Cache memory #
AMD Ryzen 5000 XT [updated]
- More models coming in the next months
- Ryzen 5 5600 XT: 6c/12t, 32 MB L3, 65 W, 3.8 GHz base #
- Ryzen 5 5600T: 6c/12t, 32 MB L3, 65 W, 3.5 GHz base #
- Vermeer #
- No iGPU #
AMD Ryzen 9000 X3D Series [added]
- Ryzen 7 9800X3D already #
- Release Date: Q1 2025 #
- Ryzen 9 9900X3D and Ryzen 9 9950X3D: 3D V-Cache on both chiplets #
- Ryzen 5 9600X3D planned #
AMD Ryzen Z2 Extreme [added]
- Release Date: Unknown #
- Designed for handheld gaming consoles #
- Core config: 3+5 #
- 3x Zen 5 and 5x Zen 5c cores #
- Based on 4 nanometer Strix Point silicon #
- RDNA 3.5 #
- LPDDR5 #
- 16 CU iGPU #
AMD Zen 5c
- Release date: Unknown
- 16 cores per CCD, in a single CCX that shares 32 MB L3 cache #
- Produced on a more advanced 3 nm node than Zen 5 #
AMD Zen 6
- Release date: Unknown
- Codename: Morpheus #
- Codename: Sound Wave #
- Codename: Medusa #
- 10% IPC increase over Zen 5 #
- New FP16 capabilities #
- 32-core CCD #
- Not sure if one CCX or two 16-core CCX's #
- Server codename: Venice #
- EPYC uses Socket SP7 #
Intel Arrow Lake "KS" [added]
Intel Bartlett Lake-S
- Release Date: Q3-2025 #
- Uses Socket LGA 1700 #
- Product by the "Network and Edge" Business group (NEX), so maybe not designed for consumers #
- Uses Intel 7 process #
- Support for DDR4 and DDR5 #
- Could be launched as "15th Gen" #
- UHD Graphics 770 integrated graphics #
- Up to 12 P-Cores, no E-Cores #
- TDPs of 125 W, 65 W and 45 W #
- Core 9: 12P, Core 7: 10P, Core 5: 8P, no Core 3 #
Intel Grand Ridge
- Release Date: Unknown, could be canceled
- Produced on 7 nm HLL+ process
- Successor to Atom "Snow Ridge"
- 24 cores across 6 clusters with 4 cores each
- 4 MB L2 per cluster, plus L3 cache
- Uses Gracemont CPU core
- Dual-channel DDR5
- PCI-Express Gen 4 with 16 lanes
Intel Arrow Lake Mobile [added]
- Release Date: Q1 2025 at CES #
- Codename: Arrow Lake-H and Arrow Lake-HX #
- Core Ultra 9 285H: 45 W, 6P, 8E, 2 LPE cores, up to 5.4 GHz, 8 cores Xe2 iGPU, 24 MB L3 #
- Core Ultra 7 265H: 28 W, 6P, 8E, 2 LPE cores, up to 5.3 GHz, 8 cores Xe2 iGPU, 24 MB L3 #
- Core Ultra 5 255H: 28 W, 6P, 8E, 2 LPE cores, up to 5.1 GHz, 8 cores Xe2 iGPU, 24 MB L3 #
- Core Ultra 3 235H: 28 W, 4P, 8E, 2 LPE cores, up to 5.0 GHz, 8 cores Xe2 iGPU, 18 MB L3 #
- Core Ultra 3 225H: 28 W, 4P, 8E, 2 LPE cores, up to 5.0 GHz, 7 cores Xe2 iGPU, 18 MB L3 #
Intel Arrow Lake Refresh [updated]
Intel Falcon Shores
- Release Date: 2025 #
- Successor to Ponte Vecchio #
- AI and HPC data center "XPU" #
- Used to be CPU+GPU, now GPU only #
- Ethernet, up to 288 GB of HBM3 at 9.8 TB/s #
- Support for FP8 and FP16 #
- Combines multiple tiles of various architectures #
- Up to 1500 W power draw #
- 5x the perf/watt and 5x more bandwidth than Ponte Vecchio #
- Won't be able to run on OAM 2.0, because that tops out at 1000 W #
Intel Twin Lake
Intel Panther Lake [updated]
- Release Date: H2 2025 or H1 2026 #
- Successor to "Lunar Lake" #
- Actual processor first displayed in Oct 2024 #
- Branded "Core Ultra 300 series" #
- iGPU features Xe3 "Celestial" graphics architecture #
- AI performance doubled #
- Uses Intel 18A process #
- Doubles the core count over Lunar Lake to 16 cores #
- Multi-tile configuration of 5 tiles. CPU and NPU in "Die 4", Platform control (PCD) in "Die 1", iGPU in "Die 5", two other tiles for structural integrity #
- Uses Xe3 "Celestial" GPU cores #
- PTL-U: 4P+0E+4LP, 4 Xe3 cores, 15 W #
- PTL-H: 4P+8E+4LP, 4 Xe3 cores, 25 W #
- Could also be 6P+8E+4LP #
- PTL-P: 4P+8E+4LP, 12 Xe3 cores, 25 W #
- Another leak says Panther Lake-H SKUs range from 4P+8E+4LP to 6P+8E+4LP, with Xe2 counts between 4 and 12 and TDP between 25 and 45 W #
- Possibly increased memory capacities (above 32 GB) #
Intel Clearwater Forest [updated]
- Release Date: 2025 #
- Intel 18A process #
- Could utilize Direct 3D Stacking technology #
- Very big chip #
- Possibly 288 E-Cores #
Intel Nova Lake [updated]
- Release Date: 2026 #
- Successor to Lunar Lake
- New P-Core "Cobra Core", could also be "Cobra Cove" to follow Intel's naming scheme #
- Uses TSMC 2 nanometer process for the CPU tile #
Intel Beast Lake [added]
NVIDIA Arm CPUs for Desktop [updated]
- Release Date: 2025 #
- NVIDIA plans to build Arm processors for use in desktop computers #
- Microsoft Windows operating system is supported #
- Targets high-end segment #
- Partnered with MediaTek #
- Uses Blackwell GPU IP #
Graphics / GPUs
NVIDIA Blackwell / GeForce RTX 50 [updated]
- Release Date: Jan 2025 (CES) #
- Most of the GeForce 50 stack will release in Q1 2025 #
- RTX 5090 and 5080: January #
- RTX 5070 and RTX 5070 Ti: February #
- RTX 5060 and RTX 5060 Ti: March #
- B200 and GB200 announced at GTC 2024 #
- GB202: 24,576 cores, 12 GPC, 8 TPC per GPC, 512-bit, 32/64 GB GDDR7 #
- GB203: 10,752 cores, 7 GPC, 6 TPC per GPC, 256-bit, 16/32 GB GDDR7 #
- GB205: 6,400 cores, 5 GPC, 5 TPC per GPC, 192-bit, 12 GB GDDR7 #
- GB206: 6,144 cores, 3 GPC, 6 TPC per GPC, 128-bit, 8/16 GB GDDR7 #
- GB207: 2,560 cores, 2 GPC, 5 TPC per GPC, 128-bit, 8/16 GB GDDR6 #
- No GB204 #
- RTX 5090: PG144/145-SKU30 GB202-300, 21760 cores, 512-bit GDDR7 32 GB, 600 W #
- RTX 5090 could require two 16-pin power connectors #
- RTX 5090D and 5080D planned for Chinese market #
- RTX 5080: PG144/147-SKU45, GB203-400, 10752 cores, 256-bit GDDR7 16 GB, 400 W #
- RTX 5060 Mobile: 8 GB GDDR7, 28 Gbps #
- Also just "B100" #
- 512-bit memory interface on flagship GPU #
- GDDR7 memory on top Blackwell GPUs #
- GDDR7 speeds up to 32 Gbps #
- Uses TSMC 3 nm process #
- GeForce 50 chips could use TSMC 5 nm process called "4N" #
- GB100 could be an MCM design #
- GB203 uses 256-bit memory interface #
- NVIDIA is testing designs with power ranges of 250 to 600 W #
- RTX 5090 uses the huge cooler that we saw in leaks for RTX 4090 Ti #
- Micron presentation suggests that RTX 5090 is +42% faster than RTX 4090 #
- B100: $30,000+ per chip, GB200 $60-$70k per unit #
- Laptop GPU: N22W #
NVIDIA Rubin
- Release Date: Q4 2025 #
- Successor to "Blackwell" #
- Named after the scientist Vera Rubin #
- Flagship GPU: R100, built on TSMC 3 nm EUV, chiplet design, CoWoS-L with HBM4 #
- Grace Ruben GR200 could be 3 nm #
AMD Radeon RX 7300 and 7400 [added]
- Release date: unknown
- Uses Navi 33 GPU #
AMD Radeon RX 7500 XT
- Release date: unknown
- Uses 6 nm Navi 33 GPU #
AMD Radeon RX 7600 XT 10 GB and 12 GB
- Release date: unknown
- PowerColor has registered such models with the EEC #
AMD Radeon RX 7650 GRE [added]
- Release date: unknown
- Based on 6 nm Navi 33 (not 5 nm Navi 32) #
- Maybe higher clocks, because Navi 33 already maxed out on RX 7600 Series #
AMD Radeon RX 7700 Non-XT
AMD Radeon RX 7800 Non-XT
AMD Radeon RX 7900 Non-XT
- Release date: unknown
- Acer filed some product names #
AMD Radeon RX 7950 XT / XTX
- Release date: unknown
- Uses Navi 31 GPU #
AMD RDNA 4 / Radeon RX 8000 Series [updated]
- Release Date: H2 2024, probably Computex #
- Uses Navi 4x GPU family
- Focus on gaming performance, without going overboard with AI #
- AMD confirms, not fighting NVIDIA for the performance crown #
- Improvements to draw calls #
- Possibly no plans for high-end GPUs, only x700 and below #
- New ray tracing engine #
- Product stack tops out at $400, but with performance similar to RX 7900 XTX #
- Only Navi 44 and Navi 43 planned #
- Other leaks talk about Navi 48: 256-bit GDDR6, 64 MB L3, 20 Gbps on XTX, 18 Gbps on XT #
- Navi 44: 48 MB L3, 192-bit, 19 Gbps GDDR6
- Navi 4x chips will use a smaller package #
- Generation codename "GFX1200" # #
- also "GFX1201" #
- Uses 16 Gbps GDDR6 memory #
- Navi 48 XTX ES spotted #
- Could be a dual-chiplet GPU #
AMD Navi 4c
- Release Date: Possibly canceled #
- Embraces chiplet design even more #
- Separate dies for Shader Engines (SED) and Multimedia & IO (MID) #
- Shader Engine Dies could be built on 3 nanometer TSMC #
- Uses an active interposer (AID) #
AMD RDNA 5
AMD UDNA [added]
- Release Date: Unknown #
- AMD is expected to unify their RDNA and CDNA architectures into a single architecture #
Intel Alchemist+ Architecture
- Release Date: 2023, probably H2 # #
- Seems to be canceled, considering it's 2024 and Intel is starting to talk about Battlemage #
- Refreshed "Alchemist" architecture #
- Could be on an improved node, better than TSMC 6 nm #
- Possibly higher core speeds with same core counts #
Intel Battlemage Architecture [updated]
- Release Date: possibly before Black Friday 2024 #
- Successor to "Alchemist" #
- New architecture #
- Newer foundry node and higher performance #
- Two variants: "Xe2 HPG" (high-performance) and "Xe2 LPG" (low-power) #
- BMG-21 GPU, also BMG-10 #
- Xe2 LPG will be first used in Meteor Lake IGP #
- Possibly only for desktop and workstation, no add-in cards for mobile #
- Xe core count doubled to 64, or 1024 EUs #
- Another leak suggests 56 Xe cores or 448 EUs #
- Clocks up to 3 GHz #
- IPC improvements and new math formats #
- Engineering sample: 20 Xe2 cores, 160 CUs, 2.85 GHz clock and 12 GB memory #
- 256-bit memory, high mem clock #
- ES running memory at 19 Gbps #
- Another leak suggests 192-bit memory #
- GPU codename: BMG-G10 # #
- Uses soldered BGA2362 #
- Two variants: BGA2362-BMG-X2 and BGA2727-BMG-X3 #
- Updated Display Engine with UHBR13.5 #
- PCI-Express 5.0 #
- Fabricated on TSMC 4 nm EUV process # # #
Intel Celestial Architecture
- Release Date: H2 2026 #
- Confirmed "in development" as of Jan 2024 #
- Discrete GPU architecture
- Successor to "Battlemage" architecture
- Also called "Xe3 HPG"
- Fabricated on TSMC N3X (3 nm) # #
- Targets "Ultra Enthusiast" segment
- 8192 shaders, 2x that of A770 #
Intel Druid Architecture
- Release Date: Not before 2027
- Discrete GPU architecture
- Successor to "Celestial" architecture
- Also called "Xe Next HPG"
Chipsets
AMD B850 / B450 Chipsets [updated]
- Release Date: 2025 #
- X870 and X870E already launched in Summer 2024
- Supports Ryzen 9000 Granite Ridge with the Zen 5 architecture #
- Same Socket AM5 as on Ryzen 7000 #
Intel 800-Series Chipsets [updated]
- Z890 already released as launch chipset for Arrow Lake
- Release Date: 2025 Q1 for lower-cost chipsets
- Chipset models: W880, Q870, B860, H810 #
- H870 canceled #
- All chipsets except for H810 have 1x x16 Gen 5 for GPU + 1x x4 Gen 5 for M.2 #
- Lanes can be split into 2x x8 or 1x x8 + 3x 4 on Q870, Z890, W880
- ECC support on W880 only #
- No memory OC on H810, Q870 #
Memory
DDR6 System Memory
- Release Date: Unknown
- Initial Draft from JEDEC: 2024 #
- Version 1.0 spec: mid-2025 #
- Four channels per module (2x that of DDR5, 4x that of DDR4) #
- 64 banks #
- Speeds starting at DDR6-8800 up to DDR6-17600 in 1st generation #
- LPDDR6 starts at LPDDR6-10667 with 24-bit channel with 2x 12-bit sub-channels #
- Maximum LPDDR6 data rate is expected to be LPDDR6-14400 #
GDDR6W Graphics Memory
- Release Date: Unknown
- Builds on Samsung's Fan-Out Wafer-Level Packaging (FOWLP) technology
- Mounts the silicon memory dies on a wafer instead of a PCB
- Up to 22 Gbps per pin
- With a 512 bit interface that would be 1.4 TB/s
- Up to 24,000 MT/s
- Could be renamed GDDR6+
GDDR7 Graphics Memory [updated]
- Release Date: H1 2024 #
- Mass production (Hynix): Q1 2025 #
- JEDEC standard published as of Mar 2024 #
- Speeds: 36,000 MT/s #
- First gen achieves 32 Gbps at 1.2 V, which is lower than the 1.35 V on GDDR6 #
- Over time up to 50,000 MT/s #
- Uses PAM3 signalling # #
- "Real-time error protection feature," maybe some kind of ECC? #
- Improved power efficiency #
- Will be used by NVIDIA GeForce 50 and AMD RDNA 4
- First products could use slower 16 or 24 Gbit speeds #
- Read clock can be configured to "always running," "disabled," "start with RCK start," "start with read" #
- 1ß production node #
- Samsung uses D1z node, 10-nm class with EUV #
- Samsung: 37 Gbps, 16 Gbit #
- 37 Gbps chip displayed at GTC 2024, 1.1 V #
- Samsung 28 Gbps and 32 Gbps chips are announced as of Mar 2024 #
- Samsung 24 Gbit GDDR7 uses 10 nanometer process, up to 40 Gbps #
- Able to issue commands in parallel #
- Micron: 16 and 24 Gbit dies, up to 32 Gbps per pin #
- Hynix: 35.4 Gbps, 16 Gbit #
- First test machines with 40 Gbps available as of Mar 2024 #
HBM3e Memory [updated]
- Release Date: H1 2024 for first shipments, bigger volume in H2 #
- Hynix: Volume production as of March 2024 #
- Hynix: 12-layer HBM 3e in mass production as of Sep 2024 #
- 16-stack introduced by Hynix in Nov 2024 #
- Same as HBM3 but with higher speeds #
- Samsung: up to 9.8 Gbps #
- Samsung will supply $3B worth of HBM3e 12H 36 GB stacks to AMD for CDNA #
- Hynix # #
- NVIDIA GB200 will use 192/384 GB of HBM3e #
HBM4 Memory [updated]
- Sampling Date: 2025 #
- NVIDIA requests faster mass production #
- Mass production: 2026 # #
- Samsung: Non-conductive film (NCF) assembly and hybrid copper bonding (HCB) #
- 2048-bit interface #
- 6000 MT/s #
- Uses a copper layer as a conductor and oxide insulator instead of regular micro bumps #
- TSMC and Hynix have formed a joint venture to develop HBM4 #
- TSMC will use 12 nm and 5 nm to produce HBM4 #
- TSMC: 12-Hi (48 GB) and 16-Hi (64 GB) stacks #
HBM4e Memory
- Mass production: 2026 #
- SK Hynix development #
- Puts memory controller at the bottom of the memory stack #
HBM-PIM Memory [added]
- Release date: Unknown
- Stands for "processing-in-memory" #
- Adds computation functions to the memory stack #
HBM5 Memory [added]
Silicon Fabrication Tech
TSMC 2 nanometer
- Release Date: Q4-2024 Risk Production #
- Mass Production in Q2-2025 #
- June 2020: TSMC is accelerating R&D
- Sep 2020: fab construction has begun
- Will use Gate-All-Around (GAA) technology
- Probable VVIP customer: Apple #
- Multi-bridge channel field effect transistor (MBCFET) architecture
- 10-15% speed improvement over N3 at same power, or 25-30% power at same speed
- Several process variants: N2, N2P and N2X
- Not using High-NA EUV #
- Nanosheet transistors
TSMC 1.4 nanometer
TSMC 1 nanometer
- Release Date: around 2030 #
- Fab construction: 2026 #
- Uses Semi-metal bismuth for contact electrodes #
- Chip plan planning has started as of Nov 2022 #
- Codename "A10" #
- Uses High-NA EUV #
Samsung 3 nanometer
- Mass Production: H12022
- "Initial production" started as of Jun 30th 2022
- Uses Gate All Around FET transistors (GAA), Multi-Bridge-Channel FET (MBCFET)
- 45% less power while delivering 23% more performance
- 35% less silicon space taken per transistor (vs. 7 nm)
- 16% less silicon space taken per transistor (vs. 5 nm)
- 2nd generation 3 nm expected in 2025, reduces power by 50%, improves perf by 30%, reduces area by 35%
- Samsung claims 60-70% yields as of May 2023 #
- In Jul 2023 Samsung claimed 60% yields, and points out that this is better than TSMC #
- According to a newer report, both Samsung and TSMC are struggling with yields for their 3 nm node #
- Trial run of second-generation 3 nm process starting in early 2024 #
Samsung 2 nanometer [updated]
- Mass production: Q1 2025 #
- Uses Multi-Bridge-Channel FET (MBCFETTM)
- Feb 2024: order received for AI chips #
- Possibly using backside power delivery #
- Efficiency improved by 25%, performance by 12%, area by 5% #
- Samsung's new Texas fab might be 2 nm #
- Capacity in S3 foundry: 7000 wafers per month #
Samsung 1.4 nanometer [updated]
- In planning as of Oct 2022
- Plant construction: Q2 2025 #
- Mass Production: 2027 or 2028 #
- GAA (gate-all-around)
- 2.5D/3D integration
- Micro-bumps
Intel 20A [updated]
- Release Date: H1 2024 #
- Cancelled for Foundry Customers #
- 20 Angstrom = 2 nanometers
- New transistors called RibbonFET
- PowerVia to connect silicon dies
- 15% perf/watt improvement over Intel 3 #
Intel 18A [updated]
- Release Date: 2025 #
- 18 Angstrom = 1.8 nanometer
- Intel expects to beat TSMC to this milestone #
- Improvements to RibbonFET for higher transistor density #
- 10% perf/watt improvement over Intel 20A #
- Feb 2024: an order for Intel 18A has been placed by Faraday Technology Corp. for an Arm-based SOC #
- Broadcom not happy with test results #
Intel 14A
- Release Date: Unknown #
- 14 Angstrom = 1.4 nanometer #
- 15% performance per watt over Intel 18A #
- 20% increase in transistor density #
- High-NA extreme ultraviolet (EUV) #
- Also 14A-E process with additional 5% performance boost #
[/spoiler]
Intel 10A
Other
Toshiba/WD 5-Bit-per-Cell NAND Flash (PLC)
- Release Date: Delayed to 2025
- Stores an additional bit of information per cell (compared to QLC)
- 32 states per cell
- Will enable even cheaper SSDs, probably at a performance cost
Toshiba XL-Flash
- Developed by Toshiba
- Uses existing SLC flash technology to improve latencies
- 1/10th the read latency of TLC
- Good for random IOPS and better QoS at shallow queue depth
- Can combine SLC and TLC/QLC for tiered, cost-optimized storage
- Intel Optane memory competitor
- 128 gigabit (Gb) die (in a 2-die, 4-die, 8-die package)
- 4 KB page size for more efficient operating system reads and writes
- 16-plane architecture for more efficient parallelism
- Fast page read and program times
Kioxia / WD 218-layer 3D NAND Flash
- Release Date: 2023 #
- Sampling as of Mar 2023 #
- Uses CMOS directly Bonded to Array technology #
- 1 Tb TLC and QLC #
- Density increased by 50% #
- 3.2 GB/s #
- 20% improvement in write performance and read latency #
Hynix 321-layer 3D NAND Flash
- Release Date: H1 2025 #
- Transfer rate increased from 164 MB/s to 194 MB/s #
- 1 Tb capacity with TLC #
- 20 Gbit/mm² #
- 41% more bit growth, 13% shorter read latency, 12% faster program performance, 10% better read power efficiency #
- 16 KB page size, 4 planes #
- 2400 MT/s #
- Made from three stack of 107-layers each #
Hynix 400-layer 3D NAND Flash [updated]
Samsung 290 layer 3D NAND Flash
- Release Date: 2024 #
- Mass Production started of 1 Tbit TLC: Apr 2024 #
- 9th generation V-NAND #
- 11 nm class process #
Samsung 280-layer 3D NAND QLC Flash
- Release Date: Unknown
- Mass Production for QLC in H2 2024 #
- Density: 1 Tbit #
- Density: 28.5 Gb/mm² at 3.2 GB/s #
Samsung 430-layer 3D NAND Flash [updated]
- Release Date: 2026 #
- Uses Bonding Vertical Technology, so separate layers can be bonded together, to improve yields #
- Up to 60% density improvement #
Samsung 1000-layer 3D NAND Flash [updated]
- Release Date: 2030 #
Intel CXL Interconnect
- New interconnect for high-bandwidth devices like CPUs, GPUs, memory
- Targeted at enterprise and servers
- Competitor to NVLink, Infinity Fabric, and PCI-Express
- Uses PCIe physical layer
- Link layer designed for low latency
- 32 Gbps per lane, per direction (like PCIe Gen 5.0)
- Samsung has announced open-source Scalable Memory Development Kit (SMDK) in Oct 2021
- CXL Memory standardized as of Jun 2024 #
PCI-Express 6.0
- Release Date: 2023
- Hardware expected: 2024
- Spec version 1.0 published as of Jan 2022
- Spec version 0.9 published as of Oct 2021
- Spec version 0.5 published as of Feb 2020
- Spec version 0.7 published as of Nov 2020
- 64 GT/s raw bit rate, up to 256 GB/s with x16
- Rambus has controller IP ready as of Jan 2022
- Rambus has PHY and controller ready as of Oct 2022
- Includes low-latency Forward Error Correction (FEC) with additional mechanisms to improve bandwidth efficiency
- Maintains backwards compatibility with all previous generations of PCIe technology
- New physical layer with PAM4 (pulse amplitude modulation) signaling replacing NRZ (non-return to zero)
PCI-Express 7.0
Dec 26th, 2024 01:46 EST
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