Introduction

In this article, which our team will regularly update, we will maintain a growing list of information pertaining to upcoming hardware releases based on leaks and official announcements as we spot them. There will obviously be a ton of rumors on unreleased hardware, and it is our goal to—based on our years of industry experience—exclude the crazy ones. In addition to these upcoming hardware release news, we will regularly adjust the structure of this article to better organize information. Each time an important change is made to this article, it will re-appear on our front page with a "new" banner, and the additions will be documented in the forum comments thread. This article will not leak information we signed an NDA for.

Feel free to share your opinions and tips in the forum comments thread and subscribe to the same thread for updates.

Last Update (Apr 3rd):

• Added AMD Ryzen 9000G
• Updated AMD Zen 5 Threadripper / Threadripper 9000
• Added AMD Ryzen 9 9955HX3D
• Added AMD Gorgon Point
• Updated AMD Zen 6
• Added NVIDIA N1X SoC
• Updated Intel Arrow Lake Refresh
• Updated Intel Wildcat Lake
• Updated Intel Panther Lake
• Updated Intel Clearwater Forest
• Updated Intel Nova Lake
• Added NVIDIA GeForce RTX 5060 Ti
• Added NVIDIA GeForce RTX 5060
• Added NVIDIA GeForce RTX 5050
• Added NVIDIA GeForce RTX 5080 24 GB
• Added NVIDIA GeForce RTX TITAN Blackwell
• Added AMD Radeon RX 9070 XT with 32 GB
• Added AMD Radeon RX 9070 GRE
• Added AMD Radeon RX 9060 XT
• Added AMD Radeon RX 9040 & RX 9050
• Added Intel High-End Battlemage
• Updated NVIDIA Rubin
• Updated Intel Celestial Architecture
• Added LPDDR5M Memory
• Updated HBM4 Memory
• Updated TSMC 2 nanometer
• Updated TSMC 1.4 nanometer
• Updated Samsung 2 nanometer
• Updated Samsung 1.4 nanometer
• Updated Intel 18A
• Added SMIC 5 nanometer
• Added Hynix HBF High-Bandwidth Flash
• Added NVIDIA SOCAMM Memory
• Added Kioxia 1000-layer 3D NAND Flash
• Updated Samsung 1000-layer 3D NAND Flash
• Added YMTC 294-layer 3D NAND Flash
• Updated PCI Express 7.0
• Removed launched products: AMD Zen 5 Mobile, AMD Ryzen 5000 XT, AMD Ryzen 9000 X3D Series, AMD Ryzen Z2 Extreme, Intel Arrow Lake Mobile, Intel Bartlett Lake, NVIDIA Blackwell / GeForce RTX 50, Radeon 7300/7400/7500/7600 10 GB, RX 7650 GRE, RX 7700 non-XT, RX 7800 non-XT, RX 7900 non-XT, RX 7950 XT / XTX, AMD RDNA 4 / RX 8000, Intel Battlemage, AMD B850 / B450 Chipsets, Intel 800-Series Chipsets, GDDR7 graphics memory,

Processors

AMD Ryzen 9000G [added]

• Release date: Q4 2025 #
• Uses Zen 5 architecture and RDNA 3.5 iGPU #
• Similar to mobile-only Strix Halo, Strix Point, Krackan Point APUs #
• Socket AM5 #
• Up to 12 cores total (4x Zen 5 + 8x Zen 5c) #
• Radeon 890M iGPU, XDNA 2 NPU #

AMD Zen 5 Threadripper / Threadripper 9000 [updated]

• Release Date: 2025 #
• Another leak suggests late 2025 #
• Codename: Shimada Peak #
• Zen 5 architecture #
• Same socket as Zen 4 Threadripper #
• 96 Cores #
• Threadripper gets support for 3D V-Cache memory #
• Threadripper 9975WX: 32c/64t #
• Threadripper 9965WX: 24c/48t #
• More models planned with 16, 64 and 96 cores #
• 32 MB L3 per CCD #
• 8-channel memory interface #
• 128 PCIe Gen 5 lanes #
• Up to 350 W TDP #

AMD Ryzen 9 9955HX3D [added]

• Release date: 2025 #
• Laptop CPU with 3D V-Cache #
• 64 MB L3 #
• 16 Zen 5 cores up to 5.4 GHz #
• 55 W to 75 W power limit #

AMD Zen 5c

• Release date: Unknown
• 16 cores per CCD, in a single CCX that shares 32 MB L3 cache #
• Produced on a more advanced 3 nm node than Zen 5 #

AMD Gorgon Point [added]

• Release date: 2026 #
• Significant 1T performance increase #
• 12 GPU cores Zen 5 / Zen 5c #
• Possibly 4x Zen 5 + 8x Zen 5c #
• iGPU based on RDNA 3.5 #
• XDNA 2 NPU, 55 TOPS #
• "Gorgon Point" is to "Strix Point" what "Hawk Point" was to "Phoenix Point" #

AMD Zen 6 [updated]

• Release date: Unknown
• Codename: Morpheus #
• Codename: Sound Wave #
• Codename: Medusa Point (laptop) #
• Medusa Point uses soldered BGA, similar in size and Z-Height as Strix Point #
• Another leak suggests bigger footprint BGA FP10 with 25 x 42.5 mm #
• Codename: Olympic Ridge (desktop) #
• Olympic Ridge supports Socket AM5 #
• 10% IPC increase over Zen 5 #
• New FP16 capabilities #
• Not sure if one CCX or two 16-core CCX's #
• Server codename: Venice #
• EPYC uses Socket SP7 #
• CCD built using 3 nm class node e.g. TSMC N3E # #
• 12 Zen 6 cores per CCD, in a single CCX, sharing an L3 cache of 48 MB #
• Another leak suggests 32-core CCD #
• Medusa Point laptops will use RDNA 4 iGPU and an updated NPU in the IO die #
• Another leak suggests RDNA 3.5 iGPU GFX1153 for Medusa and RDNA 4 for Olympic #
• Could possibly introduce low power island CCX with Zen 6c #
• iGPU has 16 CUs #
• 3D V-Cache works the same as on Zen 5 #
• IO die is expected to be built using Samsung 4LPP # #
• Higher memory speeds supported at 1:1, over 10 GT/s with 1:2 #
• CUDIMM support #

NVIDIA N1X SoC [added]

• Announcement: Computex 2025 #
• Release Date: Q4 2025 #
• Arm architecture #
• Will be used on upcoming Windows on Arm laptops #
• MediaTek collaboration #
• Blackwell architecture#
• N1x and N1 (non-X) #
• 180-200 AI TOPS #
• Volume: 3 million units #

Intel Arrow Lake "KS"

• Release Date: 2025 at least #
• Could be called Core Ultra 9 295K #

Intel Grand Ridge

• Release Date: Unknown, could be canceled
• Produced on 7 nm HLL+ process
• Successor to Atom "Snow Ridge"
• 24 cores across 6 clusters with 4 cores each
• 4 MB L2 per cluster, plus L3 cache
• Uses Gracemont CPU core
• Dual-channel DDR5
• PCI Express Gen 4 with 16 lanes
• Sources

  
  www.techpowerup.com/270718/intel-readies-atom-grand-ridge-24-core-processor-features-pcie-4-0-and-ddr5
  

Intel Arrow Lake Refresh [updated]

• Release Date: Late 2025 # #
• Only for K and KF SKUs #
• Could be canceled #
• Or resurrected #
• Adds NPU inside SOC tile #
• 48 TOPS NPU #
• 125 W TDP #
• Could be called Core Ultra 300 (and Nova Lake becomes Core Ultra 400) #
• Socket LGA 1851 #

Intel Falcon Shores

• Canceled as of Jan 2025 #
• Successor to Ponte Vecchio #
• AI and HPC data center "XPU" #
• Used to be CPU+GPU, now GPU only #
• Ethernet, up to 288 GB of HBM3 at 9.8 TB/s #
• Support for FP8 and FP16 #
• Combines multiple tiles of various architectures #
• Up to 1500 W power draw #
• 5x the perf/watt and 5x more bandwidth than Ponte Vecchio #
• Won't be able to run on OAM 2.0, because that tops out at 1000 W #

Intel Wildcat Lake [updated]

• Release Date: 2025 #
• Abbreviated WCL #
• Successor to Alder Lake-N #
• Targets lightweight laptops and mini-PCs #
• Soldered BGA 1516 socket, 35x25 mm #
• 18A process #
• 2P + 4LPE configuration #
• Cougar Cove P-Cores, Darkmont LPE cores #
• Thunderbolt 4 #
• LPDDR5X memory #
• Leaked model: 2P+0E+4LP+2Xe3, 40 TOPS #

Intel Twin Lake

• Release Date: Unknown #
• Successor to "Alder Lake N" #
• E-Cores only, using "Skymont" architecture #

Intel Panther Lake [updated]

• Release Date: H2 2025 or H1 2026 # # #
• Intel's new CEO commits to H2 2025 #
• Successor to "Lunar Lake" #
• Actual processor first displayed in Oct 2024 #
• Powering on as of Dec 2024 #
• Uses Cougar Cove P-Cores and Skymont E-Cores, four LPE cores #
• Branded "Core Ultra 300 series" #
• iGPU features Xe3 "Celestial" graphics architecture #
• iGPU with 12 CU #
• AI performance doubled #
• Uses Intel 18A process #
• Doubles the core count over Lunar Lake to 16 cores #
• Memory support LPDDR5X exclusively #
• Multi-tile configuration of 5 tiles. CPU and NPU in "Die 4", Platform control (PCD) in "Die 1", iGPU in "Die 5", two other tiles for structural integrity #
• Uses Xe3 "Celestial" GPU cores #
• PTL-U: 4P+0E+4LP, 4 Xe3 cores, 15 W #
• PTL-H: 4P+8E+4LP, 4 Xe3 cores, 25 W #
• Could also be 6P+8E+4LP #
• Another leak suggests 25 W PL1 and 64 W PL2 #
• Secondary PTL-H configs could be 4P+8E+4LP+4Xe3 and a 4P+0E+4LP+4Xe3 #
• Entry-level configs run at 15 W PL1 and 44 W PL2 in baseline mode, scaling to 25 W PL1 and 55 W PL2 in performance mode #
• PTL-P: 4P+8E+4LP, 12 Xe3 cores, 25 W #
• Another leak says Panther Lake-H SKUs range from 4P+8E+4LP to 6P+8E+4LP, with Xe2 counts between 4 and 12 and TDP between 25 and 45 W #
• Possibly increased memory capacities (above 32 GB) #
• Panther Lake will be used in future Intel-base handheld gaming PCs #
• Thunderbolt 4 supported #

Intel Clearwater Forest [updated]

• Release Date: H1 2026 #
• Intel 18A process #
• Could utilize Direct 3D Stacking technology #
• Very big chip #
• Possibly 288 E-Cores #

Intel Nova Lake [updated]

• Release Date: 2026 #
• Engineering samples ready as of Feb 2025 #
• Successor to Arrow Lake
• New P-Core "Cobra Core," could also be "Cobra Cove" to follow Intel's naming scheme #
• Other leak: 16 Coyote Cove P-Cores and 32 Arctic Wolf E-Cores and 4 LPE cores #
• Also considering 28-core (8P + 16E + 4LPE), and 16-core (4P + 8E + 4LPE) SKUs #
• Up to 52 cores #
• NVL-SK: 2x (8P+16E), NVL-HX: 1x (8P+16E), NVL-S/NVL-H: 4P+8E, NVL-U: 4P+OE #
• Possibly 4-core variant for low power laptops #
• Unlike Lunar Lake, no on-package memory #
• Uses TSMC 2 nanometer process for the CPU tile #
• Should be "quite a jump from Arrow Lake (ARL) in terms of MT performance" #
• Also using Intel 14 A #
• DDR5 memory #
• PCI Express 6.0 #

Intel Beast Lake

• Release Date: 2026 or 2027 #
• Successor to Arrow Lake #
• Uses Royal Core 1.1 P-Core architecture #

NVIDIA Arm CPUs for Desktop

• Release Date: 2025 #
• NVIDIA plans to build Arm processors for use in desktop computers #
• Microsoft Windows operating system is supported #
• Targets high-end segment #
• Partnered with MediaTek #
• Uses Blackwell GPU IP #

Graphics / GPUs

NVIDIA GeForce RTX 5060 Ti [added]

• Release Date: April 16, 2025 #
• 16 GB and 8 GB models # #
• 28 Gbps, 128-bit GDDR7 memory #
• GB206-300-A1 GPU #
• PG152-SKU10/15 boards #
• 4608 cores #
• 2407 MHz base clock, 2572 MHz boost #
• 180 W TDP #
• Majority of models will use 16-pin power connector #
• 4299 RMB #
• Could be a PCIe Gen 5 x8 design #

NVIDIA GeForce RTX 5060 [added]

• Release Date: May 2025 #
• Based on GB206-250-A1 GPU #
• PG152-SKU25 board #
• 3840 cores (30 SM) #
• 8 GB VRAM only #
• Some rumors about 16 GB versions were fake #
• 128-bit GDDR7, 28 Gbps #
• 150 W TDP #
• 3799 RMB #
• Might use standard 8-pin power connectors #
• Could be a PCIe Gen 5 x8 design #

NVIDIA GeForce RTX 5050 [added]

• Release Date: 2025
• Another leak suggests April 2025 #
• 2560 cores #
• 8 GB VRAM #
• GDDR6 128-bit #
• 135 W TDP #
• Another leak suggests 130 W TDP #
• DLSS4 Multi-Frame-Generation #
• GB207-300-A1 / PG152-SKU50 #
• Zotac models #
• Sub-$300 price point #

NVIDIA GeForce RTX 5080 24 GB [added]

• Release Date: Unknown #
• 24 GB VRAM instead of 16 GB #
• Using 3 GB GDDR7 memory chips #
• Could be a typo by MSI #
• Could also be held back for RTX 5080 SUPER #

NVIDIA GeForce RTX TITAN Blackwell [added]

• Release Date: Unknown #
• GB202-200-A1 GPU #
• Could use the full GB202 GPU #
• 24,576 CUDA cores, 768 Tensor cores, 192 RT cores, 768 TMUs, and 192 ROPs, besides 88 MB of L2 cache #
• 512-bit GDDR7 memory interface #
• 32 Gbps memory speeds #
• Two 12V-2x6 power connectors #

AMD Radeon RX 9070 XT with 32 GB [added]

• Release Date: Q2 2025 #
• Uses 32 GB VRAM instead of 16 GB #
• Would require 16 2 GB memory chips, i.e. on both sides of the PCB #
• AMD's Frank Azor debunked these rumors #
• But rumors resurfaced #

AMD Radeon RX 9070 GRE [added]

• Release Date: 2025, probably Q2 or Computex #
• Used Navi 48 GPU (same as 9070 non-XT/XT) #
• 12 GB VRAM #
• GRE now stands for "Great Radeon Edition" #
• 192-bit GDDR6 #

AMD Radeon RX 9060 XT [added]

• Release Date: Q2 2025 #
• 16 GB and 8 GB models # #
• Official teaser #
• Performance could reach RTX 4070 #
• ASUS: TUF, PRIME and DUAL #
• Acer: Nitro, BiFrost #
• 20 Gbps GDDR6 with 128-bit interface #
• 12 GB VRAM #
• Navi 44 GPU #
• 1x HDMI 2.1, 2x DP 2.1 #
• 150 W / 200 W TBP #
• Priced around $400 #
• Another report says $350 to $450 #

AMD Radeon RX 9040 & RX 9050 [added]

• Release Date: Unknown #

Intel High-End Battlemage [added]

• Release Date: Probably 2025
• Uses BMG-G31 GPU #
• The lower end of the stack was launched in late 2024/2025 (Arc B580/B570) #
• Rumored that these were canceled in 2024 #
• 24 GB VRAM model based on BMG-G21, same as B580 #
• Could be called B750, B770 and B780 #

NVIDIA Rubin [updated]

• Release Date: 2026 #
• Successor to "Blackwell" #
• Named after the scientist Vera Rubin #
• Flagship GPU: R100, built on TSMC 3 nm EUV, chiplet design, CoWoS-L with HBM4 #
• Grace Ruben GR200 could be 3 nm #
• 8 stacks of HBM4 #
• NVLink 6 switches with 3600 GB/s #

AMD Navi 4c

• Release Date: Possibly canceled #
• Embraces chiplet design even more #
• Separate dies for Shader Engines (SED) and Multimedia & IO (MID) #
• Shader Engine Dies could be built on 3 nanometer TSMC #
• Uses an active interposer (AID) #

AMD RDNA 5

• Release Date: Unknown #
• Clean sheet design #
• Might not even have "RDNA" branding #

AMD UDNA

• Release Date: Unknown #
• AMD is expected to unify their RDNA and CDNA architectures into a single architecture #

Intel Celestial Architecture [updated]

• Release Date: H2 2026 #
• Could also be released in 2025 #
• Confirmed "in development" as of Jan 2024 #
• Discrete GPU architecture
• Successor to "Battlemage" architecture
• Also called "Xe3 HPG"
• dGPU might be based on Xe3P instead of Xe3 #
• Fabricated on TSMC N3X (3 nm) # #
• Could also be fabricated using Intel in-house process #
• Targets "Ultra Enthusiast" segment
• 8192 shaders, 2x that of A770 #
• Sources

  
  www.techpowerup.com/292208/intel-targeting-2024-for-ultra-enthusiast-arc-celestial-gpus
  www.techpowerup.com/285760/intel-xe-hpg-graphics-architecture-and-arc-alchemist-gpu-detailed
  

Intel Druid Architecture

• Release Date: Not before 2027
• Discrete GPU architecture
• Successor to "Celestial" architecture
• Also called "Xe Next HPG"
• Sources

  
  www.techpowerup.com/285760/intel-xe-hpg-graphics-architecture-and-arc-alchemist-gpu-detailed
  

Chipsets

Memory

LPDDR5M Memory [added]

• Release Date: Unknown #
• Developed by Hynix #
• More power efficient than LPDDR5X #
• 0.98 V #

DDR6 System Memory

• Release Date: Unknown
• Initial Draft from JEDEC: 2024 #
• Version 1.0 spec: mid-2025 #
• Four channels per module (2x that of DDR5, 4x that of DDR4) #
• 64 banks #
• Speeds starting at DDR6-8800 up to DDR6-17600 in 1st generation #
• LPDDR6 starts at LPDDR6-10667 with 24-bit channel with 2x 12-bit sub-channels #
• Maximum LPDDR6 data rate is expected to be LPDDR6-14400 #

GDDR6W Graphics Memory

• Release Date: Unknown
• Builds on Samsung's Fan-Out Wafer-Level Packaging (FOWLP) technology
• Mounts the silicon memory dies on a wafer instead of a PCB
• Up to 22 Gbps per pin
• With a 512 bit interface that would be 1.4 TB/s
• Up to 24,000 MT/s
• Could be renamed GDDR6+
• Sources

  
  www.techpowerup.com/301573/samsung-develops-gddr6w-memory-standard-double-the-bandwidth-and-density-of-gddr6-through-packaging-innovations

HBM3e Memory

• Release Date: H1 2024 for first shipments, bigger volume in H2 #
• Hynix: Volume production as of March 2024 #
• Hynix: 12-layer HBM 3e in mass production as of Sep 2024 #
• 16-stack introduced by Hynix in Nov 2024 #
• Same as HBM3 but with higher speeds #
• Samsung: up to 9.8 Gbps #
• Samsung will supply $3B worth of HBM3e 12H 36 GB stacks to AMD for CDNA #
• Hynix # #
• NVIDIA GB200 will use 192/384 GB of HBM3e #

HBM4 Memory [updated]

• Sampling Date: 2025 #
• NVIDIA requests faster mass production #
• Mass production: 2026 # #
• Samsung: Non-conductive film (NCF) assembly and hybrid copper bonding (HCB) #
• Hynix tapeout in Q4 2024 #
• Hynix in March 2025: 12-layer HBM4 samples shipped with 36 GB capacity #
• 2048-bit interface #
• 6000 MT/s #
• Uses a copper layer as a conductor and oxide insulator instead of regular micro bumps #
• TSMC and Hynix have formed a joint venture to develop HBM4 #
• TSMC will use 12 nm and 5 nm to produce HBM4 #
• TSMC: 12-Hi (48 GB) and 16-Hi (64 GB) stacks #

HBM4e Memory

• Mass production: 2026 #
• SK Hynix development #
• Puts memory controller at the bottom of the memory stack #

HBM-PIM Memory

• Release date: Unknown
• Stands for "processing-in-memory" #
• Adds computation functions to the memory stack #

HBM5 Memory

• Release date: Unknown
• 20hi stack #
• Possibly using of Hybrid Bonding Technology #

Silicon Fabrication Tech

TSMC 2 nanometer [updated]

• Release Date: Q4-2024 Risk Production #
• Trial run in Q1 2025: very successful #
• Mass Production in Q1-2026 #
• June 2020: TSMC is accelerating R&D
• Sep 2020: fab construction has begun
• Capacity end of 2025: up to 80,000 wafers per month #
• 2026: 125,000 wafers per month #
• Will use Gate-All-Around (GAA) technology
• Probable VVIP customer: Apple #
• First batch fully reserved for Apple #
• Other customers: NVIDIA, AMD and Broadcom #
• Multi-bridge channel field effect transistor (MBCFET) architecture
• 10-15% speed improvement over N3 at same power, or 25-30% power at same speed
• Several process variants: N2, N2P and N2X
• Not using High-NA EUV #
• Nanosheet transistors

TSMC 1.4 nanometer [updated]

• Risk Trial Production: 2027 #
• Mass Production: 2028 #
• Ahead of schedule as of Apr 2025 #
• Codename "A14" #
• Not using High-NA EUV #

TSMC 1 nanometer

• Release Date: around 2030 #
• Fab construction: 2026 #
• Uses Semi-metal bismuth for contact electrodes #
• Chip plan planning has started as of Nov 2022 #
• Codename "A10" #
• Uses High-NA EUV #

Samsung 3 nanometer

• Mass Production: H12022
• "Initial production" started as of Jun 30th 2022
• Uses Gate All Around FET transistors (GAA), Multi-Bridge-Channel FET (MBCFET)
• 45% less power while delivering 23% more performance
• 35% less silicon space taken per transistor (vs. 7 nm)
• 16% less silicon space taken per transistor (vs. 5 nm)
• 2nd generation 3 nm expected in 2025, reduces power by 50%, improves perf by 30%, reduces area by 35%
• Samsung claims 60-70% yields as of May 2023 #
• In Jul 2023 Samsung claimed 60% yields, and points out that this is better than TSMC #
• According to a newer report, both Samsung and TSMC are struggling with yields for their 3 nm node #
• Trial run of second-generation 3 nm process starting in early 2024 #
• Sources

  
  www.techpowerup.com/296345/samsung-begins-chip-production-using-3nm-process-technology-with-gaa-architecture
  www.techpowerup.com/287565/samsung-foundry-announces-gaa-ready-3nm-in-2022-2nm-in-2025-other-speciality-nodes
  www.techpowerup.com/283983/samsung-3-nm-gaafet-node-delayed-to-2024
  www.techpowerup.com/266368/samsung-to-commence-5nm-euv-mass-production-in-q2-2020-develop-3nm-gaafet-node
  www.techpowerup.com/265751/samsung-to-deliver-3-nm-manufacturing-process-in-2022-with-next-generation-transistors
  

Samsung 2 nanometer [updated]

• Mass production: Q4 2025 #
• Uses Multi-Bridge-Channel FET (MBCFETTM)
• Feb 2024: order received for AI chips #
• Possibly using backside power delivery #
• Efficiency improved by 25%, performance by 12%, area by 5% #
• Samsung's new Texas fab might be 2 nm #
• Capacity in S3 foundry: 7000 wafers per month #
• Sources

  
  www.techpowerup.com/287565/samsung-foundry-announces-gaa-ready-3nm-in-2022-2nm-in-2025-other-speciality-nodes
  

Samsung 1.4 nanometer [updated]

• In planning as of Oct 2022
• Plant construction: Q2 2025 #
• Mass Production: 2027 or 2028 #
• Could be canceled as of Mar 2025 #
• GAA (gate-all-around)
• 2.5D/3D integration
• Micro-bumps
• Sources

  
  www.techpowerup.com/299538/samsung-electronics-unveils-plans-for-1-4-nm-process-technology
  

Intel 20A

• Release Date: H1 2024 #
• Cancelled for Foundry Customers #
• 20 Angstrom = 2 nanometers
• New transistors called RibbonFET
• PowerVia to connect silicon dies
• 15% perf/watt improvement over Intel 3 #
• Sources

  
  www.techpowerup.com/305596/intel-20a-and-18a-foundry-nodes-complete-development-phase-on-track-for-2024-manufacturing
  www.techpowerup.com/284936/intel-rebadges-10nm-enhanced-superfin-node-as-intel-7-invents-other-creative-node-names
  

Intel 18A [updated]

• Release Date: H2 2025 #
• First wafers produced in Arizona as of March 2025 #
• Risk production as of April 2025 #
• 18 Angstrom = 1.8 nanometer
• Intel expects to beat TSMC to this milestone #
• Improvements to RibbonFET for higher transistor density #
• 10% perf/watt improvement over Intel 20A #
• Feb 2024: an order for Intel 18A has been placed by Faraday Technology Corp. for an Arm-based SOC #
• NVIDIA and Broadcom testing 18 A #
• Broadcom not happy with test results #
• Density similar to TSMC #
• Backside power delivery #
• Sources

  
  www.techpowerup.com/305596/intel-20a-and-18a-foundry-nodes-complete-development-phase-on-track-for-2024-manufacturing
  www.techpowerup.com/292126/intel-tick-tock-alive-again-company-announces-new-intel-18a-node-1-8-nm-class
  

Intel 14A

• Release Date: Unknown #
• 14 Angstrom = 1.4 nanometer #
• 15% performance per watt over Intel 18A #
• 20% increase in transistor density #
• High-NA extreme ultraviolet (EUV) #
• Also 14A-E process with additional 5% performance boost #

Intel 10A

• Release Date: end of 2027 #
• 10 Angstrom = 1 nanometer #

SMIC 5 nanometer [added]

• Release Date: 2025 #
• Difficult due to readily available EUV equipment in China #
• 40-50% more expensive than TSMC #

Other

Hynix HBF High-Bandwidth Flash [added]

• Release Date: Unknown #
• New memory architecture that comes 3D NAND storage with HBM-like bandwidth #
• 16 BiCS8 dies stacked #
• 4 TB memory usable like VRAM #
• pSLC #

NVIDIA SOCAMM Memory [added]

• Release Date: Unknown #
• Developed by NVIDIA #
• System On Chip Advanced Memory Module—SOCAMM #
• Adapts CAMM for higher memory density #
• 694 I/O pins vs 644 on LPCAMM and 260 on DRAM #
• LPDDR5X substrate integration #
• Partners: SK Hynix, Samsung, Micron #

Toshiba/WD 5-Bit-per-Cell NAND Flash (PLC)

• Release Date: Delayed to 2025
• Stores an additional bit of information per cell (compared to QLC)
• 32 states per cell
• Will enable even cheaper SSDs, probably at a performance cost
• Sources

  
  www.techpowerup.com/283337/western-digital-may-introduce-penta-layer-cell-plc-nand-by-2025
  www.techpowerup.com/258650/toshiba-talks-about-5-bit-per-cell-plc-flash-memory
  

Toshiba XL-Flash

• Developed by Toshiba
• Uses existing SLC flash technology to improve latencies
• 1/10th the read latency of TLC
• Good for random IOPS and better QoS at shallow queue depth
• Can combine SLC and TLC/QLC for tiered, cost-optimized storage
• Intel Optane memory competitor
• 128 gigabit (Gb) die (in a 2-die, 4-die, 8-die package)
• 4 KB page size for more efficient operating system reads and writes
• 16-plane architecture for more efficient parallelism
• Fast page read and program times
• Sources

  
  www.techpowerup.com/257904/toshiba-memory-introduces-xl-flash-storage-class-memory-solution
  www.techpowerup.com/246611/toshiba-looks-to-take-on-optane-with-xl-flash-low-latency-3d-nand-technology
  

Kioxia / WD 218-layer 3D NAND Flash

• Release Date: 2023 #
• Sampling as of Mar 2023 #
• Uses CMOS directly Bonded to Array technology #
• 1 Tb TLC and QLC #
• Density increased by 50% #
• 3.2 GB/s #
• 20% improvement in write performance and read latency #

Hynix 321-layer 3D NAND Flash

• Release Date: H1 2025 #
• Transfer rate increased from 164 MB/s to 194 MB/s #
• 1 Tb capacity with TLC #
• 20 Gbit/mm² #
• 41% more bit growth, 13% shorter read latency, 12% faster program performance, 10% better read power efficiency #
• 16 KB page size, 4 planes #
• 2400 MT/s #
• Made from three stack of 107-layers each #

Hynix 400-layer 3D NAND Flash

• Release Date: 2025 Q4 #
• Uses Hybrid Bonding Technology #

Samsung 290 layer 3D NAND Flash

• Release Date: 2024 #
• Mass Production started of 1 Tbit TLC: Apr 2024 #
• 9th generation V-NAND #
• 11 nm class process #

Samsung 280-layer 3D NAND QLC Flash

• Release Date: Unknown
• Mass Production for QLC in H2 2024 #
• Density: 1 Tbit #
• Density: 28.5 Gb/mm² at 3.2 GB/s #

Samsung 430-layer 3D NAND Flash

• Release Date: 2026 #
• Uses Bonding Vertical Technology, so separate layers can be bonded together, to improve yields #
• Up to 60% density improvement #

Kioxia 1000-layer 3D NAND Flash [added]

• Release Date: 2027 #
• QLC and PLC #

Samsung 1000-layer 3D NAND Flash [updated]

• Release Date: 2030 #
• Multi-BV NAND design #
• Stacks four wafers to overcome structural limits #

YMTC 294-layer 3D NAND Flash [added]

• Shipping as of Jan 2025 #
• TLC #
• 232 active layers #
• Uses hybrid bonding #
• XTacking 4.0 #

CXL Interconnect

• New interconnect for high-bandwidth devices like CPUs, GPUs, memory
• Targeted at enterprise and servers
• Competitor to NVLink, Infinity Fabric, and PCI Express
• Uses PCIe physical layer
• Link layer designed for low latency
• 32 Gbps per lane, per direction (like PCIe Gen 5.0)
• Samsung has announced open-source Scalable Memory Development Kit (SMDK) in Oct 2021
• CXL Memory standardized as of Jun 2024 #
• Sources

  
  www.techpowerup.com/287564/samsung-introduces-industrys-first-open-source-software-solution-for-cxl-memory-platform
  www.techpowerup.com/254462/intel-reveals-the-what-and-why-of-cxl-interconnect-its-answer-to-nvlink
  www.techpowerup.com/253534/intel-releases-compute-express-link-cxl-1-0-new-interconnect-protocol-that-enables-pcie-gen-5-0
  

PCI Express 6.0

• Release Date: 2023
• Hardware expected: 2024
• Spec version 1.0 published as of Jan 2022
• Spec version 0.9 published as of Oct 2021
• Spec version 0.5 published as of Feb 2020
• Spec version 0.7 published as of Nov 2020
• 64 GT/s raw bit rate, up to 256 GB/s with x16
• Rambus has controller IP ready as of Jan 2022
• Rambus has PHY and controller ready as of Oct 2022
• Includes low-latency Forward Error Correction (FEC) with additional mechanisms to improve bandwidth efficiency
• Maintains backwards compatibility with all previous generations of PCIe technology
• New physical layer with PAM4 (pulse amplitude modulation) signaling replacing NRZ (non-return to zero)
• Sources

  
  www.techpowerup.com/300225/rambus-delivers-pcie-6-0-interface-subsystem-for-high-performance-data-center-and-ai-socs
  www.techpowerup.com/291356/rambus-delivers-pcie-6-0-controller-for-next-generation-data-centers
  www.techpowerup.com/290805/pci-sig-releases-pcie-6-0-specification-64-gt-s-per-lane
  www.techpowerup.com/287573/pci-sig-announces-pcie-6-0-final-draft-specification
  www.techpowerup.com/274253/pcie-6-0-specification-reaches-milestone-remains-on-track-for-a-2021-release
  www.techpowerup.com/264172/pci-express-gen-6-reaches-development-milestone-on-track-for-2021-rollout
  www.techpowerup.com/260177/pci-express-gen-6-0-specification-to-finalize-by-2021
  www.techpowerup.com/256634/pci-sig-announces-pcie-6-0-specification
  

PCI Express 7.0 [updated]

• Release Date: 2025 #
• Version 0.3 released as of Jun 2023 #
• Version 0.5 released as of Apr 2024 #
• Version 0.7 released as of Jan 2025 #
• Version 0.9 released as of Mar 2025 #
• Spec is work in process as of 2022
• 128 GT/s raw bit rate, up to 512 GB/s with x16 #
• PAM4 signaling #
• Improved power efficiency #
• Backwards compatible with all previous versions of PCIe #