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Netac NV5000 500 GB (TenaFe TC2200 + YMTC CDT1B)

500 GB
Capacity
TC2200
Controller
TLC
Flash
PCIe 4.0 x4
Interface
M.2 2280
Form Factor

Multiple hardware versions found.

Performance could vary due to unannounced flash/controller changes.

SSD Controller
Controller
NAND Die
NAND Die
The Netac NV5000 is a solid-state drive in the M.2 2280 form factor, launched in 2023. It is available in capacities ranging from 500 GB to 1 TB. This page reports specifications for the 500 GB variant. With the rest of the system, the Netac NV5000 interfaces using a PCI-Express 4.0 x4 connection. The SSD controller is the TC2200 Merak from TenaFE, a DRAM cache is not available. Netac has installed 128-layer TLC NAND flash on the NV5000, the flash chips are made by YMTC. Please note that this SSD is sold in multiple variants with different NAND flash or controller, which could affect performance, the "Notes" section at the end of this page has more info. To improve write speeds, a pseudo-SLC cache is used, so bursts of incoming writes are absorbed more quickly. Thanks to support for the fast PCI-Express 4.0 interface, performance is excellent. The NV5000 is rated for sequential read speeds of up to 4,800 MB/s and 2,700 MB/s write; random IO reaches 200K IOPS for read and 440K for writes.
The SSD's price at launch is unknown. The warranty length is set to five years, which is an excellent warranty period. Netac guarantees an endurance rating of 320 TBW, a typical value for consumer SSDs.

Solid-State-Drive

Capacity: 500 GB
Variants: 500 GB 1 TB
Hardware Versions:
Overprovisioning: 46.3 GB / 10.0 %
Production: Active
Released: 2023
Part Number: NT01NV5000-500G-E4X
Market: Consumer

Physical

Form Factor: M.2 2280 (Single-Sided)
Interface: PCIe 4.0 x4
Protocol: NVMe 1.4
Power Draw: Unknown

Controller

Manufacturer: TenaFE
Name: TC2200 Merak
Architecture: ARM 32-bit Cortex-M7
Core Count: Dual-Core
Foundry: TSMC FinFET
Process: 12 nm
Flash Channels: 4 @ 1,600 MT/s
Chip Enables: 4
Controller Features: HMB (enabled)

NAND Flash

Manufacturer: YMTC
Name: Xtacking 2.0 (CDT1B)
Type: TLC
Technology: 128-layer
Speed: 1600 MT/s
Capacity: 4 chips @ 2 Tbit
ONFI: 4.1
Topology: Charge Trap
Die Size: 60 mm²
(8.5 Gbit/mm²)
Dies per Chip: 4 dies @ 512 Gbit
Planes per Die: 4
Decks per Die: 2
Word Lines: 141 per NAND String
90.8% Vertical Efficiency
Read Time (tR): 50 µs
Program Time (tProg): 620 µs
Block Erase Time (tBERS): 9.0 ms
Die Read Speed: 1280 MB/s
Die Write Speed: 70 MB/s
Endurance:
(up to)
3000 P/E Cycles
Page Size: 16 KB
Block Size: 2304 Pages
Plane Size: 1980 Blocks

DRAM Cache

Type: None
Host-Memory-Buffer (HMB): 64 MB

Performance

Sequential Read: 4,800 MB/s
Sequential Write: 2,700 MB/s
Random Read: 200,000 IOPS
Random Write: 440,000 IOPS
Endurance: 320 TBW
Warranty: 5 Years
MTBF: 2.0 Million Hours
Drive Writes Per Day (DWPD): 0.4
SLC Write Cache: Yes

Features

TRIM: Yes
SMART: Yes
Power Loss Protection: No
Encryption:
  • No
RGB Lighting: No
PS5 Compatible: Yes

Same Drive

This section lists other SSDs in our database using the exact same hardware components

Notes

NAND Die:

Read Time (tR): Maximum is 50 µs, typical is lower
Typical Program Time (tPROG): 620 µs
Maximum Program Time (tPROG): Maximum is 910 µs
Block Erase Time (tBERS): Maximum is 20 ms, typical is lower
Array Eficiency of over 92%
YMTC 128L Xtacking 2.0 cell architecture consists of two decks connected through deck-interface buffer layer which is the same process with KIOXIA 112L BiCS 3D NAND structure. Cell size, CSL pitch, and 9-hole VC layouts keep the same design and dimension (horizontal/vertical WL and BL pitches) with previous 64L Xtacking 1.0 cell. Total number of gates is 141 (141T) including selectors and dummy WLs for the TLC operation.
This layout has a 1x 4 Plane layout, each one lineup side by side

Nov 7th, 2024 14:25 EST change timezone

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