NAND Die:
Die read speed: aproximation
Die write speed: aproximation
In order to enable a balanced Gray data encoding, all five pages of data are needed in
both the first and second pass of the program algorithm. While this is the norm for most
QLC implementations except [1], it requires the storage of a few megabytes of data per
die in a DRAM or similar media. Instead, we use a 1b/cell (SLC) cache on the NAND die
to store the data needed for the two-pass PLC programming algorithm. To keep the area
overhead of the SLC cache to less than 2%, we improved the SLC reliability to 250k
program/erase (P/E) cycles, commensurate with 1k of P/E cycle capability in the present
PLC work.