According to the latest report from Bloomberg, the US government under Joe Biden's administration has announced plans to provide Taiwan Semiconductor Manufacturing Company (TSMC) with a substantial financial support package worth $11.6 billion. The package is composed of $6.6 billion in grants and up to $5 billion in loans. This represents the most significant financial assistance approved under the CHIPS and Science Act, a key initiative to resurrect the US chip industry. The funding will aid TSMC in establishing three cutting-edge semiconductor production facilities in Arizona, with the company's total investment in the state expected to exceed an impressive $65 billion. TSMC's multi-phase Arizona project will commence with the construction of a fab module near its existing Fab 21 facility. Production using 4 nm and 5 nm process nodes is slated to begin by early 2025. The second phase, scheduled for 2028, will focus on even more advanced 2 nm and 3 nm technologies.

TSMC has kept details about the third facility's production timeline and process node under wraps. The company's massive investment in Arizona is expected to profoundly impact the local economy, creating 6,000 high-tech manufacturing jobs and over 20,000 construction positions. Moreover, $50 million has been earmarked for training local workers, which aligns with President Joe Biden's goal of bolstering domestic manufacturing and technological independence. However, TSMC's Arizona projects have encountered obstacles, including labor disputes and uncertainties regarding government support, resulting in delays for the second facility's production timeline. Additionally, reports suggest that at least one TSMC supplier has abandoned plans to set up operations in Arizona due to workforce-related challenges.

Intel Core Ultra "Lunar Lake-MX" will be the company's bulwark against Apple's M-series Pro and Max chips, designed to power the next crop of performance ultraportables. The MX codename extension denotes MoP (memory-on-package), which sees stacked LPDDR5X memory chips share the package's fiberglass substrate with the chip, to conserve PCB footprint, and give Intel greater control over the right kind of memory speed, timings, and power-management features suited to its microarchitecture. This is essentially what Apple does with its M-series SoCs powering its MacBooks and iPad Pros. Igor's Lab scored the motherlode on the way Intel has restructured the various components across its chiplets, and the various I/O wired to the package.

When compared to "Meteor Lake," the "Lunar Lake" microarchitecture sees a small amount of "re-aggregation" of the various logic-heavy components of the processor. On "Meteor Lake," the CPU cores and the iGPU sat on separate tiles—Compute tile and Graphics tile, respectively, with a large SoC tile sitting between them, and a smaller I/O tile that serves as an extension of the SoC tile. All four tiles sat on top of a Foveros base tile, which is essentially an interposer—a silicon die that facilitates high-density microscopic wiring between the various tiles that are placed on top of it. With "Lunar Lake," there are only two tiles—the Compute tile, and the SoC tile.

The 3 nm EUV node, which will be TSMC's final semiconductor fabrication node to implement FinFET transistors, will make for a staggering 20% of TSMC's revenues in 2024, a report by ICSmart says. 20% is big for a new foundry node, considering that TSMC is simultaneously running 4 nm and 5 nm EUV nodes; 6 nm and 7 nm DUV nodes; and several older mature nodes. Apple is expected to be the foundry's biggest customer for 3 nm, as it could power the company's current A17 and M3, and upcoming A18 and M4 line of chips for its next-generation iPhone and MacBooks; followed by NVIDIA, AMD, and possibly even Intel. AMD is expected to build some versions of its upcoming "Zen 5" processors on 3 nm; while Intel is expected to use 3 nm for some of the tiles of its upcoming "Lunar Lake" processor. The same report goes to suggest that 3 nm will make up 30% of TSMC's revenues in 2025.

Ahead of the 2024 Optical Fiber Communication Conference (OFC), MediaTek (last week) announced it is launching a next-generation custom ASIC design platform that includes the heterogeneous integration of both high-speed electrical and optical I/Os in the same ASIC implementation. MediaTek will be demonstrating a serviceable socketed implementation that combines 8x800G electrical links and 8x800G optical links for a more flexible deployment. It integrates both MediaTek's in-house SerDes for electrical I/O as well as co-packaged Odin optical engines from Ranovus for optical I/O. Leveraging the heterogeneous solution that includes both 112G LR SerDes and optical modules, this CPO demonstration delivers reduced board space and device costs, boosts bandwidth density, and lowers system power by up to 50% compared to existing solutions.

Additionally, Ranovus' Odin optical engine has the option to provide either internal or external laser optical modules to better align with practical usage scenarios. MediaTek's ASIC experience and capabilities in the 3 nm advanced process, 2.5D and 3D advanced packaging, thermal management, and reliability, combined with optical experience, makes it possible for customers to access the latest technology for high-performance computing (HPC), AI/ML and data center networking.

One key takeaway from the ongoing GTC is that Nvidia's AI empire has taken shape with strong partnerships from TSMC and other Taiwanese makers, such as those major server ODMs.

According to the news report from the technology-focused media DIGITIMES Asia, during his keynote at GTC on March 18, Huang underscored his company's partnerships with TSMC, as well as the supply chain in Taiwan. Speaking to the press later, Huang said Nvidia will have a very strong demand for CoWoS, the advanced packaging services TSMC offers.

NVIDIA has been offering its GPU IP for more than a decade now ever since the introduction of Kepler uArch, and its IP has had relatively low traction in other SoCs. However, that trend seems to be reaching an inflection point as NVIDIA has given MediaTek a license to use its GPU IP to produce the next generation of processors for the auto industry. The newest MediaTek Dimensity Auto Cockpit family consists of CX-1, CY-1, CM-1, and CV-1, where the CX-1 targets premium vehicles, CM targets medium range, and CV targets lower-end vehicles, probably divided by their compute capabilities. The Dimensity Auto Cockpit family is brimming with the latest technology, as the processor core of choice is an Armv9-based design paired with "next-generation" NVIDIA GPU IP, possibly referring to Blackwell, capable of doing ray tracing and DLSS 3, powered by RTX and DLA.

The SoC is supposed to integrate a lot of technology to lower BOM costs of auto manufacturing, and it includes silicon for controlling displays, cameras (advanced HDR ISP), audio streams (multiple audio DSPs), and connectivity (WiFi networking). Interestingly, the SKUs can play movies with AI-enhanced video and support AAA gaming. MediaTek touts the Dimensity Auto Cockpit family with fully local AI processing capabilities, without requiring assistance from outside servers via WiFi, and 3D spatial sensing with driver and occupant monitoring, gaze-aware UI, and natural controls. All of that fits into an SoC fabricated at TSMC's fab on a 3 nm process and runs on the industry-established NVIDIA DRIVE OS.

ASML celebrated an important milestone last week—the company's social media account shared news about their third generation extreme ultraviolet (EUV) lithography tool reaching an unnamed customer: "chipmakers have a need for speed! The first Twinscan NXE:3800E is now being installed in a chip fab. 🔧 With its new wafer stages, the system will deliver leading edge productivity for printing advanced chips. We're pushing lithography to new limits." The post included a couple of snaps—ASML workers were gathered in front of a pair of climatized containers, and Peter Wennink (President and CEO) and Christophe Fouquet (EVP and CBO) thanked staff at company HQ.

The Twinscan NXE:3800E is ASML's latest platform from a series of 0.33 numerical aperture (Low-NA) lithography scanners. Information is scarce—the company has not yet published a 3800E product page. The preceding model—Twinscan NXE:3600D—supports EUV volume production at 3 and 5 nm. ASML roadmaps imply that the Twinscan NXE:3800E has been designed to produce chips on 2 and 3 nm-class technologies. The company's cutting-edge High-NA extreme ultraviolet (EUV) chipmaking tools (High-NA Twinscan EXE) are expected to cost around $380 million—reports from last month point to a possible $183 million price point for "existing Low-NA EUV lithography systems." Another Low-NA EUV machine is reported to be lined up for a possible 2026 release window—ASML's next-gen Twinscan NXE:4000F model will co-exist alongside emerging (pricier) High-NA solutions.

The latest TrendForce report reveals a notable 7.9% jump in 4Q23 revenue for the world's top ten semiconductor foundries, reaching $30.49 billion. This growth is primarily driven by sustained demand for smartphone components, such as mid and low-end smartphone APs and peripheral PMICs. The launch season for Apple's latest devices also significantly contributed, fueling shipments for the A17 chipset and associated peripheral ICs, including OLED DDIs, CIS, and PMICs. TSMC's premium 3 nm process notably enhanced its revenue contribution, pushing its global market share past the 60% threshold this quarter.

TrendForce remarks that 2023 was a challenging year for foundries, marked by high inventory levels across the supply chain, a weak global economy, and a slow recovery in the Chinese market. These factors led to a downward cycle in the industry, with the top ten foundries experiencing a 13.6% annual drop as revenue reached just $111.54 billion. Nevertheless, 2024 promises a brighter outlook, with AI-driven demand expected to boost annual revenue by 12% to $125.24 billion. TSMC, benefiting from steady advanced process orders, is poised to far exceed the industry average in growth.

SMIC, China's largest semiconductor manufacturer, is reportedly assembling a dedicated team to develop 3 nm semiconductor node technology, following reports of the company setting up 5 nm chip production for Huawei later this year. This move is part of SMIC's efforts to achieve independence from foreign companies and reduce its reliance on US technology. According to a report from Joongang, SMIC's initial goal is to commence operations of its 5 nm production line, which will mass-produce Huawei chipsets for various products, including AI silicon. However, SMIC is already looking beyond the 5 nm node. The company has assembled an internal research and development team to begin work on the next-generation 3 nm node.

The Chinese manufacturer is expected to accomplish this using existing DUV machinery, as ASML, the sole supplier of advanced EUV technology, is prohibited from providing equipment to Chinese companies due to US restrictions. It is reported that one of the biggest challenges facing SMIC is the potential for low yields and high production costs. The company is seeking substantial subsidies from the Chinese government to overcome these obstacles. Receiving government subsidies will be crucial for SMIC, especially considering that its 5 nm chips are expected to be up to 50 percent more expensive than TSMC's due to the use of older DUV equipment. The first 3 nm wafers from SMIC are not expected to roll out for several years, as the company will prioritize the commercialization of Huawei's 5 nm chips. This ambitious undertaking by SMIC represents a significant challenge for the company as it strives to reduce its dependence on foreign semiconductor technology and establish itself as an essential player in the global manufacturing industry.

In a move that could intensify competition with Intel in the cutting-edge chip manufacturing space, Samsung Foundry has reportedly decided to rebrand its second-generation 3 nm-class fabrication technology, previously known as SF3, to a 2 nm-class manufacturing process called SF2. According to reports from ZDNet, the renaming of Samsung's SF3 to SF2 is likely an attempt by the South Korean tech giant to simplify its process nomenclature and better compete against Intel Foundry, at least visually. Intel is set to roll out its Intel 20A production node, a 2 nm-class technology, later this year. The reports suggest that Samsung has already notified its customers about the changes in its roadmap and the renaming of SF3 to SF2. Significantly, the company has reportedly gone as far as re-signing contracts with customers initially intended to use the SF3 production node.

"We were informed by Samsung Electronics that the 2nd generation 3 nm [name] is being changed to 2 nm," an unnamed source noted to ZDNet. "We had contracted Samsung Foundry for the 2nd generation 3 nm production last year, but we recently revised the contract to change the name to 2 nm." Despite the name change, Samsung's SF3, now called SF2, has not undergone any actual process technology alterations. This suggests that the renaming is primarily a marketing move, as using a different process technology would require customers to rework their chip designs entirely. Samsung intends to start manufacturing chips based on the newly named SF2 process in the second half of 2024. The SF2 technology, which employs gate-all-around (GAA) transistors that Samsung brands as Multi-Bridge-Channel Field Effect Transistors (MBCFET), does not feature a backside power delivery network (BSPDN), a significant advantage of Intel's 20A process. Samsung Foundry has not officially confirmed the renaming.

Some of the earliest signs are emerging that AMD's mobile processor or desktop APU silicon that succeeds "Strix Point" being codenamed "Sound Wave." AMD tends to come up with quirky internal codenames for upcoming projects, mostly to zero in on the source of leaks, so "Sound Wave" as a codename is subject to change with time. While the upcoming 4 nm "Strix Point" and "Strix Halo" chips implement the "Zen 5" CPU microarchitecture and RDNA 3+ graphics architecture, besides XDNA 2 based NPU with a generational tripling in AI TOPS; Wccftech believes that "Sound Wave" could be an AMD processor of comparable class to "Strix Point," which implements the "Zen 6" CPU microarchitecture, which AMD has planned for a 2025-26 timeframe.

Perhaps the most interesting aspect of this leak is the foundry node, with the original source over at Korean tech blog Gamma0burst referencing 3 nm. This is the final node family from TSMC to implement FinFET transistors before the foundry transitions to nanosheets with N2. It's likely that AMD chooses one of the more advanced variants of TSMC's 3 nm nodes, such as the N3P or N3X, because 2025-26 will see rival Intel get close to introducing the Intel 20A foundry node for mass-production. Not much else is known about "Sound Wave" besides the "Zen 6" CPU cores at this point.

Intel CEO Pat Gelsinger engaged with press/media representatives following the conclusion of his IFS Direct Connect 2024 keynote speech—when asked about Team Blue's ongoing relationship with TSMC, he confirmed that their manufacturing agreement has advanced from "5 nm to 3 nm." According to a China Times news article: "Gelsinger also confirmed the expansion of orders to TSMC, confirming that TSMC will hold orders for Intel's Arrow and Lunar Lake CPU, GPU, and NPU chips this year, and will produce them using the N3B process, officially ushering in the Intel notebook platform that the outside world has been waiting for many years." Past leaks have indicated that Intel's Arrow Lake processor family will have CPU tiles based on their in-house 20A process, while TSMC takes care of the GPU tile aspect with their 3 nm N3 process node.

That generation is expected to launch later this year—the now "officially confirmed" upgrade to 3 nm should produce pleasing performance and efficiency improvements. The current crop of Core Ultra "Meteor Lake" mobile processors has struggled with the latter, especially when compared to rivals. Lunar Lake is marked down for a 2025 launch window, so some aspects of its internal workings remain a mystery—Gelsinger has confirmed that TSMC's N3B is in the picture, but no official source has disclosed their in-house manufacturing choice(s) for LNL chips. Wccftech believes that Lunar Lake will: "utilize the same P-Core (Lion Cove) and brand-new E-Core (Skymont) core architecture which are expected to be fabricated on the 20A node. But that might also be limited to the CPU tile. The GPU tile will be a significant upgrade over the Meteor Lake and Arrow Lake CPUs since Lunar Lake ditches Alchemist and goes for the next-gen graphics architecture codenamed "Battlemage" (AKA Xe2-LPG)." Late January whispers pointed to Intel and TSMC partnering up on a 2 nanometer process for the "Nova Lake" processor generation—perhaps a very distant prospect (2026).

AMD is reportedly building its upcoming "Zen 5" and "Zen 5c" CPU Core Dies (CCDs) on two different foundry nodes, a report by Chinese publication UDN, claims. The Zen 5 CCD powering the upcoming Ryzen "Granite Ridge" desktop processors, "Fire Range" mobile processors, and EPYC "Turin" server processors, will be reportedly built on the 4 nm EUV foundry node, a slightly more advanced node than the current 5 nm EUV the company is building "Zen 4" CCDs on. The "Zen 5c" CCD, or the chiplet with purely "Zen 5c" cores in a high density configuration; on the other hand, will be built on an even more advanced 3 nm EUV foundry node, the report says. Both CCDs will go into mass production in Q2-2024, with product launches expected across the second half of the year.

The "Zen 5c" chiplet has a mammoth 32 cores spread across two CCXs of 16 cores, each. Each CCX has 16 cores sharing a 32 MB L3 cache. It is to cram these 32 cores, each with 1 MB of L2 cache; and a total of 64 MB of L3 cache, that AMD could be turning to the 3 nm foundry node. Another reason could be voltages. If "Zen 4c" is anything to go by, the "Zen 5c" core is a highly compacted variant of "Zen 5," which operates at a lower voltage band than its larger sibling, without any change in IPC or instruction sets. The decision to go with 3 nm could be a move aimed at increasing clock speeds at those lower voltages, in a bid to generationally improve performance using clock speeds, besides IPC and core count. The EPYC processor with "Zen 5c" chiplets will feature no more than six such large CCDs, for a maximum core count of 192. The regular "Zen 5" CCD has just 8 cores in a single CCX, with 32 MB of L3 cache shared among the cores; and TSV provision for 3D Vertical Cache, to increase the L3 cache in special variants.

ASML has revealed that its cutting-edge High-NA extreme ultraviolet (EUV) chipmaking tools, called High-NA Twinscan EXE, will cost around $380 million each—over twice as much as its existing Low-NA EUV lithography systems that cost about $183 million. The company has taken 10-20 initial orders from the likes of Intel and SK Hynix and plans to manufacture 20 High-NA systems annually by 2028 to meet demand. The High-NA EUV technology represents a major breakthrough, enabling an improved 8 nm imprint resolution compared to 13 nm with current Low-NA EUV tools. This allows chipmakers to produce transistors that are nearly 1.7 times smaller, translating to a threefold increase in transistor density on chips. Attaining this level of precision is critical for manufacturing sub-3 nm chips, an industry goal for 2025-2026. It also eliminates the need for complex double patterning techniques required presently.

However, superior performance comes at a cost - literally and figuratively. The hefty $380 million price tag for each High-NA system introduces financial challenges for chipmakers. Additionally, the larger High-NA tools require completely reconfiguring chip fabrication facilities. Their halved imaging field also necessitates rethinking chip designs. As a result, adoption timelines differ across companies - Intel intends to deploy High-NA EUV at an advanced 1.8 nm (18A) node, while TSMC is taking a more conservative approach, potentially implementing it only in 2030 and not rushing the use of these lithography machines, as the company's nodes are already developing well and on time. Interestingly, the installation process of ASML's High-NA Twinscan EXE 150,000-kilogram system required 250 crates, 250 engineers, and six months to complete. So, production is as equally complex as the installation and operation of this delicate machinery.

The sneak peeks from the upcoming IEEE Solid State Circuit Conference continues, as the agenda items unveil interesting tech that will be either unveiled or demonstrated there. Intel, Synopsys, and Marvell, are leading providers of DRAM physical layer interface (PHY) IP. Various processor, GPU, and SoC manufacturers license PHY and memory controller IP from these companies, to integrate with their designs. All three companies are ready with over 200 Gbps around the 2.69 to 3 petajoule per bit range. This energy cost is as important as the data-rate on offer; as it showcases the viability of the PHY for a specific application (for example, a smartphone SoC has to conduct its memory sub-system at a vastly more constrained energy budget compared to an HPC processor).

Intel is the first in the pack to showcase a 224 Gbps sub-picojoule/bit PHY transmitter that supports PAM4 and PAM6 signaling, and is designed for 3 nm-class FinFET foundry nodes. If you recall, Intel 3 will be the company's final FinFET node before it transitions to nanosheets with the Intel 20A node. At the physical layer, all digital memory signal is analogue, and Intel's IP focuses on the DAC aspect of the PHY. Next up, is a somewhat similar transceiver IP by Synopsys. This too claims 224 Gbps speeds at 3 pJ/b, but at a 40 dB insertion loss; and is designed for 3 nm class FinFET nodes such as the TSMC N3 family and Intel 3. Samsung's 3 nm node uses the incompatible GAAFET technology for its 3 nm EUV node. Lastly, there's Marvell, with a 212 Gb/s DSP-based transceiver for optical direct-detect applications on the 5 nm FinFET nodes, which is relevant for high speed network switching fabrics.

A DigiTimes Asia report posits that TSMC is preparing another VVIP foundry lane for Apple Inc.—insiders claim that the Taiwanese foundry giant is in the process of expanding production capacity into next generation 2 nm nanometer fields. This expensive and time consuming endeavor is only made possible with the reassurance of big customers being added to the foundry's order books. TSMC's 2 nm-class N2, N2P, and N2X process technologies are due in 2025 and beyond (according to recent presentation slides)—these advanced packages are set to drop with all sorts of innovations: nanosheet gate-all-around (GAA) transistors, backside power delivery, and super-high-performance metal-insulator-metal (SHPMIM). According to a DigiTimes source "Apple is widely believed to be the initial client to utilize the (next-gen) process."

Apple and NVIDIA were reported to be ahead of many important clients in the queue for TSMC's 3 nm process nodes, so it is not surprising to see old patterns repeat (according to industry rumors) again. Apple is expected to update its next generation iPhones, iPad, and Mac laptop product lines with more advanced Bionic and M-series chipsets in 2025. Last year's roster included a rollout of 3 nm TSMC silicon across Apple A17 Pro and M3 ARM-based processors.

MediaTek revealed its (now current generation) flagship Dimensity 9300 flagship mobile processor last November, but we are already hearing about its successor's foundation. Digital Chat Station published some early insights on their Weibo micro-blog—the tipster appears to have an inside track at MediaTek's system-on-chip R&D department. The imaginatively named "Dimensity 9400" chipset is reportedly earmarked for mass production chez TSMC, with the foundry's second generation 3 Nm process being the favored node—this information aligns with official announcements as well as industry rumors from last autumn. MediaTek's Dimensity 9300 sports a "one-of-a-kind All Big Core design," with no provision for puny efficiency units—built on TSMC's third generation 4 nm process with four ARM Cortex-X4 cores (going up to 3.25 GHz) and four Cortex-A720 cores (maximum 2.0 GHz).

Digital Chat Station reckons that the 9300's All Big Core configuration will carryover to its next generation sibling, albeit with some major upgrades. MediaTek hardware engineers are alleged to have selected ARM's latest and greatest CPU and Mali GPU designs—the Cortex-X5 core could be a prime candidate in the first category. The rumor mill has the next batch of flagship Exynos SoCs utilizing ARM's fifth generation design. Digital Chat Station proposes that more smartphone manufacturers could adopt a top-flight Dimensity 2024 chip, if its performance can match the closest rivals. Industry experts posit both MediaTek and Qualcomm choosing TSMC's N3E process for their upcoming flagship chipsets—this node apparently "offers improved cost-effectiveness and superior yields" when compared to the first generation N3B process (as ordered by Apple for its latest M and B-series SoCs). Dimensity 9400 is expected to take on Snapdragon 8 Gen 4—this could be a tough fight, given that Qualcomm's offering is set to debut with custom Oryon cores.

TSMC's Fab 21 Phase 2 facility is currently under construction in the Greater Phoenix area, Arizona—this secondary production facility was originally announced as housing a 3 nm process production line (opening by 2026), but that company target will be missed by a sizable margin. The transcription of the company's Q4 2023 Earnings Call presents another set of shifted expectations—outgoing CEO, Dr. Mark Liu—admitted that a number of factors are expected to delay Phase 2's opening by another year or two: "The second fab shell is under construction, but what technology [to use] in that shell is still under discussion...I think that also has to do with how much incentives that fab, the U.S. Government can provide…The current planning [for the fab] is '27 or '28, that will be timeframe."

Industry analysts believe TSMC leadership have a tough choice to make—the second Arizona factory's delayed launch could provide enough lead time to upgrade with a more advanced node (e.g. 2 nm), but ambitions could be lowered for the troubled site. An older plus more mature fabrication process could be a better fit, although the neighboring Fab 21 Phase 1 site is already set for a full 2025 initiation on 4 nm FinFET. Liu outlined this challenge: "To be honest, most of the overseas fabs, what technology is being set up, really, it is a decision of customers' demand in that area at that timing. So, nothing is definitive, but we are trying to optimize value for the overseas fab for TSMC." The current chairman will not be around for Phase 1's full deployment, but he shared some positive Arizona-related news: "We are well on track for volume production of N4, or 4 nm process technology, in the first half of 2025 [in Arizona] and are confident that once we begin operations, we will be able to deliver the same level of manufacturing quality and reliability in Arizona as from our fabs in Taiwan."

TSMC's 2 nm-class foundry node, dubbed N2, will enter mass production only in 2025, a report by the Financial Times says. The premier Taiwan-based foundry has been reportedly showcasing TSMC N2 to its biggest customer for advanced nodes, Apple. The node will likely power Apple's in-house silicon that drives the iPhone 17 Pro and Pro Max devices that are slated for 2025. This implies that the current 3 nm class nodes from TSMC will continue to power Apple silicon into 2024 and its iPhone 16 Pro/Pro Max.

The current Apple A17 Pro and M3 chips powering the iPhone 15 Pro/Max and the H2-2023 Macs are based on TSMC's N3 node, with a 183 MTr/mm² transistor density. TSMC has four other 3 nm-class nodes, with the N3E node that just entered mass production to offer a jump to 215.6 MTr/mm², and its 2024 successor, the N3P, pushing transistor densities further up to 224 MTr/mm². TSMC's first 2 nm-class node, the N2, offers a jump to around 259 MTr/mm², which makes the N3P a nice halfway point for Apple between the N3 and N2, for its 2024 silicon.

Dai Nippon Printing Co., Ltd. (DNP) has successfully developed a photomask manufacturing process capable of accommodating the 3-nanometer (10-9 meter) lithography process that supports Extreme Ultra-Violet (EUV) lithography, the cutting-edge process for semiconductor manufacturing.

Background
DNP has continually responded to the demands of semiconductor manufacturers in terms of performance and quality. In 2016, we became the world's first merchant photomask manufacturer to introduce the multi-beam mask writing tool (MBMW). In 2020, we developed a photomask manufacturing process for 5 nm EUV lithography processes, and have been supplying masks that meet the needs of the semiconductor market. In this latest development, in order to meet the needs of further miniaturization, we have developed a photomask for EUV lithography capable of supporting 3 nm processes.

TrendForce's research indicates a dynamic third quarter for the global foundry industry, marked by an uptick in urgent orders for smartphone and notebook components. This surge was fueled by healthy inventory levels and the release of new iPhone and Android devices in 2H23. Despite persisting inflation risks and market uncertainties, these orders were predominantly executed as rush orders. Additionally, TSMC and Samsung's high-cost 3 nm manufacturing process had a positive impact on revenues, driving the 3Q23 value of the top ten global foundries to approximately US$28.29 billion—a 7.9% QoQ increase.

Looking ahead to 4Q23, the anticipation of year-end festive demand is expected to sustain the inflow of urgent orders for smartphones and laptops, particularly for smartphone components. Although the end-user market is yet to fully recover, pre-sales season stockpiling for Chinese Android smartphones appears to be slightly better than expected, with demand for mid-to-low range 5G and 4G phone APs and continued interest in new iPhone models. This scenario suggests a continued upward trend for the top ten global foundries in Q4, potentially exceeding the growth rate seen in Q3.

Apple has announced a partnership deal with Amkor, one of the leading chip packaging and testing manufacturers, which will build a two billion US Dollar silicon packaging facility in Peoria, Arizona. Being the only US-based OSAT (outsourced semiconductor assembly and test) provider, Amkor has decided to invest its funds and apply for the CHIPS Act, hoping to get a part of the funding from the US government's grant budget. The state-of-the-art facility in Arizona will feature over 500,000 square feet (46,452 square meters) of cleanroom space for packaging and testing chips. Using Amkor's latest technologies, the plant will support advanced computing, automotive, and communications chip packaging. It is tailored to meet the capacity needs of major customer Apple starting in 2025-2026. Apple will be the largest customer, with the Amkor facility packaging Apple-designed chips produced at the nearby TSMC wafer fabrication plant.

Building a chip packaging facility in the US with advanced packaging types means that the domestic manufacturing of advanced silicon is now possible across almost the entire supply chain, with OSAT now being present on US soil as well. In the initial phase, this partnership will enable domestic advanced packaging capabilities for leading-edge chips down to 3 nm nodes, which Apple plans to utilize for its A and M series of processors. Along with the creation of an estimated 2,000 local jobs, the investment serves as a boost to the local economy as well. Additionally, Amkor is TSMC's strategic partner, meaning future designs and packaging will cooperate without any delays.

Samsung Electronics today reported financial results for the third quarter ended September 30, 2023. Total consolidated revenue was KRW 67.40 trillion, a 12% increase from the previous quarter, mainly due to new smartphone releases and higher sales of premium display products. Operating profit rose sequentially to KRW 2.43 trillion based on strong sales of flagship models in mobile and strong demand for displays, as losses at the Device Solutions (DS) Division narrowed.

The Memory Business reduced losses sequentially as sales of high valued-added products and average selling prices somewhat increased. Earnings in system semiconductors were impacted by a delay in demand recovery for major applications, but the Foundry Business posted a new quarterly high for new backlog from design wins. The mobile panel business reported a significant increase in earnings on the back of new flagship model releases by major customers, while the large panel business narrowed losses in the quarter. The Device eXperience (DX) Division achieved solid results due to robust sales of premium smartphones and TVs. Revenue at the Networks Business declined in major overseas markets as mobile operators scaled back investments.

According to Korean business news publication ChosunBiz, both Samsung and TSMC are struggling with their 3 nm node yields. The two companies have different approaches to their 3 nm nodes, with Samsung using GAA FET (Gate All Around), whereas TSMC is continuing with its FinFET technology. That said, TSMC has at least five known 3 nm nodes, of which two should be in production by now, assuming N3E has proved to be reliable enough to kick off. Samsung on the other hand has three known 3 nm nodes, with only one in production so far, called 3GAE.

ChosunBiz reports that neither company is getting the kind of yields that you'd expect from a node that should have been in volume production for around a year by now, with Samsung apparently being somewhat better than TSMC. At 60 and 50 percent respectively, neither Samsung nor TSMC are anywhere near decent yields. Anything below 70 percent is considered very poor and even the 60 percent claim in Samsungs case, is apparently limited to some kind of Chinese mining ASIC and doesn't include the SRAM you find in most modern processors. ChosunBiz also mentions a source familiar with Samsung's foundry business who mentions a yield closer to 50 percent for the company. The same source also mentions that Samsung needs to reach at least 70 percent yield to be able to attract major customers to its 3 nm node.

A couple of slides from AMD's internal presentation were leaked to the web by Moore's Law is Dead, referencing what's allegedly the next-generation "Zen 5" microarchitecture. Internally, the performance variant of the "Zen 5" core is referred to as "Nirvana," and the CCD chiplet (CPU core die) based on "Nirvana" cores, is codenamed "Eldora." These CCDs will make up either the company's Ryzen "Granite Ridge" desktop processors, or EPYC "Turin" server processors. The cores themselves could also be part of the company's next-generation mobile processors, as part of heterogenous CCXs (CPU core complex), next to "Zen 5c" low-power cores.

In broad strokes, AMD describes "Zen 5" as introducing a 10% to 15% IPC increase over the current "Zen 4." The core will feature a larger 48 KB L1D cache, compared to the current 32 KB. As for the core itself, it features an 8-wide dispatch from the micro-op queue, compared to the 6-wide dispatch of "Zen 4." The integer execution stage gets 6 ALUs, compared to the current 4. The floating point unit gets FP-512 capabilities. Perhaps the biggest announcement is that AMD has increased the maximum cores per CCX from 8 to 16. At this point we don't know if it means that "Eldora" CCD will have 16 cores, or whether it means that the cloud-specific CCD with 16 "Zen 5c" cores will have 16 cores within a single CCX, rather than spread across two CCXs with smaller L3 caches. AMD is leveraging the TSMC 4 nm EUV node for "Eldora," the mobile processor based on "Zen 5" could be based on the more advanced TSMC 3 nm EUV node.