seronxThere are two cores in there beyond belief I proved it hahahaha mwaahahaha

...and a shared floating point unit. And what appears to be shared L1 cache. So, two gimped cores. Not full hardware duplication. Just like it's always been. This is my fears validated.

seronxregmedia.co.uk/2011/02/24/amd-bulldozer-core-module.jpg

AMD Bulldozer module

There are two cores in there beyond belief I proved it hahahaha mwaahahaha :laugh:

One decode and fetch unit == 1 core? Haha!

PLease I don't want to enter this discussion, I just pointed out the obvious on that picture.

DeerSteak...and a shared floating point unit. And what appears to be shared L1 cache. So, two gimped cores.

L1D isn't shared, L1S is

The FPU unit is FMA thus allows to shoot out 2x128bit SSE FPs
and 1x256 if 1 core needs it

ThefumigatorNow I get it. If in the yields a module is defective, the whole module should be disabled. This means BD could be 2, 4, 6 and 8 cores, and there could not be triple core, unless the defect affects one core. The module itself resambles an Athlon 7000, (for those who forgot them, there were phenom 1 based dual cores with 2MB L3.

I'm a little worried about the size of the "cores". They look terribly small...

It is modular in design

BenetanegiaOne decode and fetch unit == 1 core? Haha!

PLease I don't want to enter this discussion, I just pointed out the obvious on that picture.

4 fetch/decode/store per cycle for 32bit

2 fetch/decode/store per cycle for 64bit

and in theory if there were registers for it

1 fetch/decode store per cycle for 128bit

LAN_deRf_HAErhem. Are we talking about ram bandwidth or cache? Intel 775 chips are also faster at super pi despite having notably less ram bandwidth than AMD chips. Doesn't this suggest the super pi discrepancy is exactly what everyone else has always blamed it on? It's simply a program that favors Intel architecture.

Cache speed and memory performance are very tightly linked together. We are talking about the combination of BOTH. Increase L3 speed, and memory bandwidth goes up with it. I can show this very simply with both AMD and Intel chips.

You can say that SPi favors Intel chips...but then again, if you want to go down that road, so do the majority of applications out there...any apps favors the faster performance on 1155. Like I posted above, I don't care, really, if an app favors one over the other...the fact of the matter is that the end user gets better performance on 1155, not how Intel really got there.

The important thing, for me as a user, is gaming performance. If Bulldozer has better game performance, then I'll be using Bulldozer in my gaming rig. If not, then Intel will stay in my gmaing rig, because it's faster.

There's no fanboyism in any of my comments, or concerns...I am a high-end user, and I require the best solution possible becuase I chose to game on triple monitors, and whoever brings me the best results for my chosen configuration, gets my cash.

After near two years with my Eyefinity rig, which began with a Crosshair III Formula, and now uses a Gigabyte P67A-UD4-B3, with many boards and CPUs between the two, I can quite confidently say that as it stands right this moment, for gaming, Intel is better. The graphs in my reviews show by how much.

Bickering about things like this is just kinda foolish...but...I have the time to do so. Which leaves me at this(which i stated earlier):

When I can go to my local store, and buy Bulldozer, I will. I will, firsthand, see who is faster, and you can bet that I'll be reporting the results here in the forums when that happens. As a gamer, gamnig is what's most important to me, and I see no gaming benchmarks..I see benchmarks that can relate to gaming perforamcne, and what I see, doesn't leave me impressed, or eager to spend my money on Bulldozer, but because I want to be sure you guys know the truth, I'll buy anyway.

seronxThe FPU unit is FMA thus allows to shoot out 2x128bit SSE FPs
and 1x256 if 1 core needs it

...while the other core waits in starvation. This is really bad news for highly-parallel apps.

DeerSteak...while the other core waits in starvation. This is really bad news for highly-parallel apps.

The application would be made for 128b AVX instead

256b will not be used

They have a chart they only expect 1% of any applications to use 256bits of AVX

LAN_deRf_HAWhy. That's marketing. It means zilch, zero, nada. I saw a speaker set once marketed as a sound explosion. I'm pretty sure sound didn't explode. Go read the marketing on the latest TUF board with that proactive armor heat neutralizer crap. Wtf does this shit even mean??? Marketing doesn't say crap about the realities of the product.

The new Sabertooth 990FX features an innovative passive heat sink solution that features exclusive CeraM!X technology and a 10-sensor system that actively monitors critical thermal points on the board to provide the best thermal management available today. Premium ceramic-coating
technology on critical components such as the MOSFET and the chipset heat sinks lead to an overall improvement in system stability. The TUF CeraM!X technology accomplishes this by enlarging the surface area with
its micro-porous surface – 50% more – to effectively dissipate heat.

The ceramic coating used in this technology has an excellent heat conduction property even when air flow is poor. In addition, CeraM!X is
heat tolerant and oxidization resistant, yielding to additional stability of the system.

The TUF Thermal Radar is the active thermal monitoring system featuring 10 hardware sensors embedded on-board for real-time thermal detection and reporting. Users can choose to take advantage of the manual controls or use the preset profiles to adjust fan speed and voltages automatically.

Read it up it doesn't prevent heat it accelerates heat dissipation

The armour it self and coating are resistant to heat meaning they don't melt when dissipating heat over time

DeerSteak...while the other core waits in starvation. This is really bad news for highly-parallel apps.

Wait. What 256-bit app do you run? Where's the 128-bit and 256-bit OS? Oh, that's right, we are still on 64-bit.

I think the times when FPU @ 256-bit config is not going to be that often for most of us.

Come on, man, you're smarter than that. You know as well as I do that it's got nothing to do with the "bitness" of the application. It's the precision of the floating point calculations, and if one core requires a 256-bit value, the other gets to wait.

edit: even the Core 2 Duo can do 128-bit SSE instructions in a single clock cycle. In 2006. When we were running 32-bit XP. And it helped performance even then.

DeerSteakCome on, man, you're smarter than that. You know as well as I do that it's got nothing to do with the "bitness" of the application. It's the precision of the floating point calculations, and if one core requires a 256-bit value, the other gets to wait.

Sure, but it's not going to happen very often, and you know THAT, too. ;) I hardly see this as a point of contention for normal users.

In HPC clusters it will be more common. Bulldozer is first and foremost a high-margin server part and an "enthusiast" part second. It's launching in the AM3+ world first because it's easier down here in "enthusiast" land, and you don't need the logic for multiple sockets to talk to one another. Start off easy.

DeerSteakIn HPC clusters it will be more common. Bulldozer is first and foremost a high-margin server part and an "enthusiast" part second. It's launching in the AM3+ world first because it's easier down here in "enthusiast" land, and you don't need the logic for multiple sockets to talk to one another. Start off easy.

We don't talk about Interlagos here mister!

We only talk about Zambezi, you hear?

and we are talking about module performances why did multiple sockets? we are talking about cores and the fpu ugh lol

Don't worry, seronx, one of your favorite tech sites has leaked Interlagos benchmarks too. ;)

And what I'm saying (because again, your reading comprehension deficiencies create an artificial language barrier) is that this half-core nonsense isn't going to fly in the server world where AMD thinks it will. And maybe they know that and maybe that's part of why Zamboni is coming first.

DeerSteakDon't worry, seronx, one of your favorite tech sites has leaked Interlagos benchmarks too. ;)

And what I'm saying (because again, your reading comprehension deficiencies create an artificial language barrier) is that this half-core nonsense isn't going to fly in the server world where AMD thinks it will. And maybe they know that and maybe that's part of why Zamboni is coming first.

www.cray.com/Products/XK6/KX6.aspx

*cough* Ahem?!

It's a full core not a half core

Prepare for TOP500!!!!! Interlagos AWAY!!

Again, we don't talk about Interlagos here mister!

--- Also

DeerSteakDon't worry, seronx, one of your favorite tech sites has leaked Interlagos benchmarks too. ;)

I saw the leak....the 4x16 Core Interlagos A1 1.8GHz finishing a F@H workload twice~ as fast as the 4x12 Core Magny Cours @ 2.5GHz

Interlagos
TPF 3min 52 seconds
Magny Cours
TPF 6mins 40 seconds

Project 6901

www.linuxforge.net/bonuscalc2.php gotta love that PPD

For those who don't think Zambezi is an 8 core processor, let me ask whether or not you believe the Deneb is a 4 core processor. If you go way back to a single core Athlon 64, you can find all the components which make up a true x86 core, and you'll see that there are quite a few things a Deneb die shares across multiple cores. A few of the shared components are the L3 Cache, the Integrated Memory Controller, and the HyperTransport link (possibly other things, too). So, OMG, Deneb "cores" share things, so it must not actually be a quad core. We should call it a single core with 4 integer/fpu/scheduler/pipelines/L1/L2/etc.

My point here, is that there has never been any standard definition of what an x86 core contains. A single Zambezi "core" may share a number of resources with the other "core" on its module, but "cores" have been sharing resources with each other since the advent of multi-core processors. The question is, how much has to be shared before one can no longer call it a "core". According to AMD, the Zambezi "cores" have retained enough that they still consider the processor and octal core processor. According to Intel, the i7 2600 has enough resources shared, that they consider it a quad core. Who's to argue with them?

This thread is immensely entertaining. I find it particularly hilarious that the AMD fanboys seem to think that Bulldozer only has to match Sandy on perf/price to be a winner. Erm, no, because (a) Ivy and LGA 2011 will be out by that time, and (b) Intel is making such a decent profit on their CPUs that they could cut their prices to the bone, thus pricing AMD out of the market entirely, and still make money.

Oooh, someone actually made one. That doesn't mean much for, you know, actual sales.

devguy - this is the first time actual computing resources are shared. Well, second. And Intel was smart - they called it "HyperThreading" and were up-front about what was going on.

Assimilator - Ivy Bridge will not be out this year. To say it will be out "by then" (assuming you mean Zambezi availability) is un-true.

Intel can't price AMD out of the market. There are too many governmental bodies, rightly or wrongly, watching their every move. There's plenty of room for faster "official" sandy bridge models, based on overclocking headroom, and you don't see them because they need AMD to live.

devguyFor those who don't think Zambezi is an 8 core processor, let me ask whether or not you believe the Deneb is a 4 core processor. If you go way back to a single core Athlon 64, you can find all the components which make up a true x86 core, and you'll see that there are quite a few things a Deneb die shares across multiple cores. A few of the shared components are the L3 Cache, the Integrated Memory Controller, and the HyperTransport link (possibly other things, too). So, OMG, Deneb "cores" share things, so it must not actually be a quad core. We should call it a single core with 4 integer/fpu/scheduler/pipelines/L1/L2/etc.

My point here, is that there has never been any standard definition of what an x86 core contains. A single Zambezi "core" may share a number of resources with the other "core" on its module, but "cores" have been sharing resources with each other since the advent of multi-core processors. The question is, how much has to be shared before one can no longer call it a "core". According to AMD, the Zambezi "cores" have retained enough that they still consider the processor and octal core processor. According to Intel, the i7 2600 has enough resources shared, that they consider it a quad core. Who's to argue with them?

Nice job thank you for your logic

AssimilatorThis thread is immensely entertaining. I find it particularly hilarious that the AMD fanboys seem to think that Bulldozer only has to match Sandy on perf/price to be a winner. Erm, no, because (a) Ivy and LGA 2011 will be out by that time, and (b) Intel is making such a decent profit on their CPUs that they could cut their prices to the bone, thus pricing AMD out of the market entirely, and still make money.

LGA 2011 is an expensive platform especially since the P1 and P2 cores are multiplier locked

Ivy Bridge is Sandy Bridge but for 22nm

DeerSteakOooh, someone actually made one. That doesn't mean much for, you know, actual sales.

They will sell lol BY MILLIONS!

DeerSteakdevguy - this is the first time actual computing resources are shared. Well, second. And Intel was smart - they called it "HyperThreading" and were up-front about what was going on.

Assimilator - Ivy Bridge will not be out this year. To say it will be out "by then" (assuming you mean Zambezi availability) is un-true.

Intel can't price AMD out of the market. There are too many governmental bodies, rightly or wrongly, watching their every move. There's plenty of room for faster "official" sandy bridge models, based on overclocking headroom, and you don't see them because they need AMD to live.

3.) Actually AMD doesn't need to exist only IBM
2.) No need for me to intervine
1a.) Hyperthreading makes 2 threads each thread has access to those shared resources and they compete to use those resources
1b.) Cluster-based Multithreading is 2 cores with equal amounts of resources and do not compete for resources

DeerSteakdevguy - this is the first time actual computing resources are shared. Well, second. And Intel was smart - they called it "HyperThreading" and were up-front about what was going on.

So, an IMC is not a resource that has to do computation of any kind (it's just some lump taking up die space)? If you look at an Athlon 64 single core, there is one IMC for one "core". If you look at Deneb, there is one IMC for four "cores". Is Deneb a quad core (even go ahead and disregard the other components the four "cores" share)?

If you think that it is, then what components must not be shared to remain a "core"? I can guarantee that whatever you come up with, AMD disagrees, and it would be nothing more than their interpretation of a "core" vs yours. There is no standard of what components make up an x86 core!

The memory controller has always been traditionally part of the north bridge. It's moving a north bridge feature onto the same silicon. By your logic, Intel's Core 2 line "shared computing resources", which is silly and disingenuous.

seronx1a.) Hyperthreading makes 2 threads each thread has access to those shared resources and they compete to use those resources
1b.) Cluster-based Multithreading is 2 cores with equal amounts of resources and do not compete for resources

Except for your arbitrary definition where they have to compete for the FPU.

repman244And people that are comparing core for core, I don't think that's a valid comparison, since the "cores" in the modules aren't very similar to the real cores that we know (and AFAIK BD "core" has less transistors than Phenom II core).

That's AMD's problem. They are advertising 4 module Bulldozer as "8 core" so when this comes back and bites them in the a$$ they'll have noone but themselves to blame, just like Intel did with the frequency figures in P4 era (high frequency with lousy performance).

faramirThat's AMD's problem. They are advertising 4 module Bulldozer as "8 core" so when this comes back and bites them in the a$$ they'll have noone but themselves to blame, just like Intel did with the frequency figures in P4 era (high frequency with lousy performance).

yes! finally! someone's seeing the light. Of course, this is your first post and it's reasonable to assume you understood before now, but still. Yes! finally!

DeerSteakThe memory controller has always been traditionally part of the north bridge. It's moving a north bridge feature onto the same silicon. By your logic, Intel's Core 2 line "shared computing resources", which is silly and disingenuous.

Is it? I am precisely trying to make you consider that. Why do you (not necessarily you personally) believe that some resources on a Core 2 Duo could be shared and still called a dual core, while some/other resources on a Zambezi cannot be shared if you want to label it an octal core? What exactly is it that cannot be shared, and where is the definition of the components of an x86 "core" that backs up that argument?

And your mention of the memory controller on the north bridge emphasizes the fact that there is no standard of what components make up an x86 core!

DeerSteakExcept for your arbitrary definition where they have to compete for the FPU.

It won't happen
It's an FMAC it can do 256bit Add+Multiply

Intel's solution is 256bit Add then 256bit Multiply (2 256bit Add or Multiply AVX commands when AMD Zambezi only needs 1 256 Add+Multiply AVX Command)

It is the same thing

faramirThat's AMD's problem. They are advertising 4 module Bulldozer as "8 core" so when this comes back and bites them in the a$$ they'll have noone but themselves to blame, just like Intel did with the frequency figures in P4 era (high frequency with lousy performance).

It is 8 cores

seronxDon't forget SSE5 and 128Bit AVX

I don't get this one

It is based by 10s actually
8100 = 3.5GHz 8110 = 3.6GHz 8120 3.7GHz and so on

SSE5 was replaced with several smaller instruction sets that were redesigned to work with AVX better. This happened right after the AMD/Intel contract was renegotiated. So SSE5 as far as the name is concerned will not be on Bulldozer.

Some reviews showed a while back (like years) if you change the name that was reported to some of the benchmark programs, you would magically get better numbers. A VIA C7 that was reported to the software as either an AMD processor or Intel process improved its memory and per-clock performance. While the performance could be justified as the VIA C7 aquired use of SSE3 at the time rather late and a patch for the software was needed. The memory performance change was just BS.

And there has been no confirmation of the naming scheme to my knowledge.