PCI-Express x1 met its match with the recent flood of devices such as 2-port SATA 6 Gbps and USB 3.0 controller chips that maintain their tiny package sizes thanks to a single-lane PCI-Express bus connection. The single-lane connection is already saturated with these kinds of devices: SATA 6 Gbps is moot with 250 MB/s per direction bandwidth of PCI-E 1.1, and could face bottlenecks with 500 MB/s of PCI-E 2.0, it is a similar case with USB 3.0 controllers. Use of PCI-Expresss x4, the bigger PCI-E bus standard, is a bad option as it increases PCI-E data pins by four times (significantly impacting chip package sizes), while eating into the limited lane budget of today's desktop chipsets.

The next best thing is PCI-Express 2.0 x2. While 2-lane PCI-Express is hypothetically possible, it has never been implemented by motherboard manufactures, neither on client, nor enterprise platforms. PCI-Express' parent organisation PCI-SIG doesn't have a slot or port specification for PCI-E x2, either. Intel seems to be of the idea that PCI-Express 2.0 x2 will provide immediate relief to manufacturers of small-footprint devices such as inexpensive third-party USB 3.0 and SATA 6 Gbps controllers, it provides a total of 2 GB/s bandwidth, 1 GB/s per direction, which greatly alleviates bandwidth bottlenecks, while not significanly increasing chip pin-counts. PCI-Express 3.0 is still in its infancy, while implementing PCI-Express 2.0 x2 is the easier, short-term solution. It will cause minimal R&D overhead on manufacturers to implement it. PCI-E 2.0 x2 will fit nicely into the limited lane budget of today's desktop chipsets.