Friday, May 22nd 2020
Intel Rocket Lake CPU Appears with 6 Cores and 12 Threads
We have been hearing a lot about Intel's Rocket Lake lineup of processors. They are supposed to be a backport of Willow Cove 10 nm core, adapted to work on a 14 nm process for better yielding. Meant to launch sometime around late 2020 or the beginning of 2021, Rocket Lake is designed to work on the now existing LGA1200 socket motherboards, which were launched just a few days ago along with Intel Comet Lake CPUs. Rocket Lake is there to supply the desktop segment and satisfy user demand, in light of lacking 10 nm offers for desktop users. The 10 nm node is going to present only on mobile/laptop and server solutions before it comes to the desktop.
In the latest report on 3D Mark, the hardware leaker TUM APISAK has found a Rocket Lake CPU running the benchmark and we get to see first specifications of the Rocket Lake-S platform. The benchmark ran on 6 core model with 12 threads, that had a base clock of 3,5 GHz. The CPU managed to boost up to 4,09 GHz, however, we are sure that these are not final clocks and the actual product should have even higher frequencies. Paired with Gen12 Xe graphics, the Rocket Lake platform could offer a very nice alternative to AMD offerings if the backport of Willow Cove goes well. Even though it is still using a 14 nm node, performance would be good. The only things that would be sacrificed (from backporting) are die space and efficiency/heat.
Source:
@TUM_APISAK (Twitter)
In the latest report on 3D Mark, the hardware leaker TUM APISAK has found a Rocket Lake CPU running the benchmark and we get to see first specifications of the Rocket Lake-S platform. The benchmark ran on 6 core model with 12 threads, that had a base clock of 3,5 GHz. The CPU managed to boost up to 4,09 GHz, however, we are sure that these are not final clocks and the actual product should have even higher frequencies. Paired with Gen12 Xe graphics, the Rocket Lake platform could offer a very nice alternative to AMD offerings if the backport of Willow Cove goes well. Even though it is still using a 14 nm node, performance would be good. The only things that would be sacrificed (from backporting) are die space and efficiency/heat.
38 Comments on Intel Rocket Lake CPU Appears with 6 Cores and 12 Threads
The term "grasping at straws" comes to mind.
Objectively, I don't think Intel's Comet Lake is all bad. After all, it is the fastest gaming processor based on conclusions from multiple reviewing sites (giving credit where credit is due). What I feel though is Intel's strategy is no different from doping by advertising a low TDP, but in the background drawing over 2x the amount. Sure they did clarify with tech savvy people that they have a PL2 that draws significantly higher power to give you the "up to" boost speed, but how many people out there are actually aware about this secondary power requirement to get them to the performance level that is advertised? While AMD used to draw the same amount of power with their Bulldozer chips, i.e. >200W, I feel at least they are honest about it by stating it on their TDP.
www.techspot.com/article/1876-4ghz-ryzen-3rd-gen-vs-core-i9/
www.sweclockers.com/test/29606-intel-core-i9-10900k-och-core-i5-10600k-comet-lake-s/21#content
Unfortunately, I don't think I have seen fixed frequency articles with nice comparable power measurements though. There are a couple 10400F videos that point out it seems to use less power when gaming compared to 3600.
Also, if Ian at AT is to be believed (and it didn't sound like speculation), the locked i5 parts are using true fully enabled 6-core dies, unlike the 10600K with its gimped and nearly half-disabled 10-core die.
Really goes to show how much of a stopgap Comet Lake-S is turning out to be. The entire lineup is focused around the 10900K and nothing else. No pulling production away from mobile by keeping top binned 6-core and 8-core dies from Coffee Lake for proper unlocked i5s and i7s. Just take the 10900K and disable more cores as you go down the product stack. The fact that the ringbus is stretched to its absolute limit shows, and is a disadvantage, however small, that the i5 and i7s are dragged into.
We will get confirmations when people start delidding the 10-series CPUs. We know they will whether it makes sense or not :)
Der8auer has done 10900K, I can't seem to find other models with a search right now.
I do think that idea of disabled-skipped cores causing the latency hops is a bit strange. Even if that is the case, the increases in latency are minor and should not matter in the larger scale of things. AT article does say Intel has done ringbuses for up to 12 cores and they have been OK. Maybe not great but OK.
As for the ringbus, in most cases there are no signs of issues with it. Gaming works just as fine from 4 to 10 cores, and most heavy multithreaded workloads are throttling long before this becomes an issue, well except perhaps for an edge case or two. There might be some point where a mesh makes more sense, but the choice of ringbus is probably due to the placement of the cores on the die more than anything. I think many are way too narrowly focused on the ringbus these days.
Bigger dies, more caches, more cores, wider cores, more complex extensions. ARM is going down the path x86 has already taken.
What exactly happens when it catches up is a good question, I guess we will see once they get there.
The short story is, recompiling for ARM isn't hard, but ARM needs to become CISC to be competitive. All x86 microarchitectures since the 90s have solved the "legacy problem" by using micro-operations. x86 will evolve (or be replaced by something) in the direction of more superscalar scaling and SIMD. At some point we will probably get new ISA features which helps facilitate superscalar scaling and resource dependencies, useful contextual information which are lost in the compilation process.
Because I can source you this, no problem: www.anandtech.com/show/14384/arm-announces-cortexa77-cpu-ip