Wednesday, April 28th 2021
AMD Zen 5 "Strix Point" Processors Rumored To Feature big.LITTLE Core Design
AMD launched the 7 nm Zen 3 microarchitecture which powers Ryzen 5000 processors in late 2020, we expect AMD to follow this up with a Zen 3+ on 6 nm later this year and a 5 nm Zen 4 in 2022. We are now beginning to receive the first rumors about the 3 nm Zen 5 architecture which is expected to launch in 2024 in Ryzen 8000 series products. The architecture is reportedly known as "Strix Point" and will be manufactured on TSMC's 3 nm node with a big.LITTLE core design similar to the upcoming Intel Alder Lake and the Apple M1. The Strix Point lineup will consist exclusively of APUs and could feature up to 8 high-performance and 4 low-performance cores which would be less than what Intel plans to offer with Alder Lake. AMD has allegedly already set graphics performance targets for the processors and that they will bring significant changes to the memory subsystem but with rumors for a product 3 years away from launch take them with a healthy dose of skepticism.
Sources:
MEOPC, Video Cardz
78 Comments on AMD Zen 5 "Strix Point" Processors Rumored To Feature big.LITTLE Core Design
It'll be interesting to see how and if x86 makes the full transition to these core configs. Software will need to catch up but that's just a universal constant at this point. The best built software framework is still half a decade behind the hardware.
Anyway, I wouldn't mind if all AMD processors would have an IGP as well.
And it doesn't even seem far fetched given what TSMC has been reporting. Damn. Puzzling indeed. Maybe this is where their APUs finally 'take off'?
there seems to be the beginnings of a transition happening
Always thought it would be neat if AMD brought back the old Phenom II on modern lithography, they would be tiny and sip power at 3-4GHz. All these procs good enough for most apps.
big.LITTLE on mobile have bigger impact than it does on desktop. I think this is a sensible step to stem ARM dominance , while still maintaining high performance side.
In 2024: it's an interesting question. The world of computing may become much more heterogeneus by then, with Arm more prominent in laptops and with more use cases that require running both x86 and Arm applications at the same time. That can be done either by means of fat binaries, translation (Arm running x86 code as well as x86 running Arm code), or processors with both kinds of cores.
PS
Alder Lake not Elder Lake ;)
AMD is a gamble with Memory and WHEAs.
Ryzen is bascially a Mr. Meeseeks on a PCB.
If there is something to keep 8 cores busy, why not switch to big cores instead, cough? Apple is doing it out of greed, so gotta be cool. #3.5mmAudioJacks
Why bother, scalpers, miners and whatever stupid thing will pop up could make future chips impossible to obtain at normal prices.
I can already see the poor performance threads from users when the magnificent Microsoft scheduler decides to do things less than perfectly
The opposite can be said whenever both companies experience issues. When it's Intel, they say "oh it'll be fixed whatever". When AMD has an issue, they go "AMD is truly incompetent". No memory or WHEA problems once I undervolted the retarded amount of overvoltage my board applied to my SoC and its derivative voltages. It was even worse on my Gigashite board.
Imagine thinking you need 1.1v on the SoC, 1.1v on both VDDGs and 1v on the VDDP for just 3600 MT/s. Gigabyte moment. Not to mention the board died on me shortly afterwards...
The scheduler has to not only pick the threads/processes that go on big vs little cores, but also pick what GHz (or MHz) to run the processor at. There's a bit of a "race to idle" problem. If you spend 1000ms running a task on a little core, you probably would use more power than if you had run the task on a big-core for 100ms and then slept for 900ms afterwards.
But if the sleep is interrupted after 500ms, your calculus changes yet again. So you need to predict the future and know when to turn on big cores (or turn them off), and same thing with when to clock little cores up or down.
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Answering these scheduling problems adequately for sizable gains in efficiency is not very easy. Its a lot easier when you have all the same kind of core: the answer in that case is simple. Just estimate the power usage per core and keep the clock as low as reasonable.
The RISC boat sailed a long time ago for Apple.