Thursday, July 20th 2023
AMD "Strix Point" Zen 5 Monolithic Silicon has a 12-core CPU?
It looks like the monolithic silicon that succeeds "Phoenix," codenamed "Strix Point," will finally introduce an increase in CPU core counts for the thin-and-light and ultraportable mobile platforms. "Strix Point" is codename for the next-generation APU die being developed at AMD, which, according to a leaked MilkyWay@Home benchmark result, comes with a 12-core/24-thread CPU.
The silicon is identified by MilkyWay@Home with the OPN "AMD Eng Sample: 100-000000994-03_N," and CPU identification string "AuthenticAMD Family 26 Model 32 Stepping 0 -> B20F00." The "Strix Point" CPU could be the second time AMD has increased CPU core-counts per CCX. From "Zen 3" onward, the company increased the cores per CCX from 4 to 8, allowing a single "Zen 3" CCX on the "Cezanne" monolithic silicon to come with 8 cores. It's highly likely that with "Zen 5," the company is increasing the cores/CCX to 12, and that "Strix Point" has one of these CCXs.
"Strix Point" processors will be branded under the Ryzen 8000 series. Besides the 12-core Zen 5 CPU, it is expected to feature an updated iGPU based on the RDNA3 Gen 2 graphics architecture, and an upgraded memory interface, with support for higher DDR5 and LPDDR5 memory speeds. It's likely that the AMD Radiance Display Engine finds its way to the silicon, as well as an updated XDNA Ryzen AI accelerator. AMD is expected to debut Zen 5 in 2024, with "Strix Point" squaring off against Intel's Core "Meteor Lake" processors.
Sources:
MilkyWay@home database, BenchLeaks (Twitter), VideoCardz
The silicon is identified by MilkyWay@Home with the OPN "AMD Eng Sample: 100-000000994-03_N," and CPU identification string "AuthenticAMD Family 26 Model 32 Stepping 0 -> B20F00." The "Strix Point" CPU could be the second time AMD has increased CPU core-counts per CCX. From "Zen 3" onward, the company increased the cores per CCX from 4 to 8, allowing a single "Zen 3" CCX on the "Cezanne" monolithic silicon to come with 8 cores. It's highly likely that with "Zen 5," the company is increasing the cores/CCX to 12, and that "Strix Point" has one of these CCXs.
45 Comments on AMD "Strix Point" Zen 5 Monolithic Silicon has a 12-core CPU?
All this got me thinking though. AMD is the only vendor NOT doing asymmetric cores. Mobile devices have it, Intel has it, Apple has it. I think AMD is going to have to do something here, or they might just lose the core race they started. Maybe them saying they have no intention of an E core is really that they will do something like the C core. Curious which one has more cache anyway, an AMD C core or an Intel E core?
So a mega APU sounds great, but what is the point if AMD can't deliver the support for it?
community.amd.com/t5/drivers-software/amd-ryzen-7-7840u-adrenaline-drivers/m-p/614112
ROGAlly/comments/154ct2p
Amd/comments/14gngoj
People have a lot of instability with those systems and as an example, report crashing and being completely unable to use the AI tools from Photoshop and/or Lighroom, which is a big ooof, in my view as part of the point of Phoenix was the hardware engine for AI stuff.It has already been months since the first Phoenix products hit the market. I think they started to come in by May? It was supposed to be before, I think but AMD had delays.
I meant in the forum here at TPU, with the key phrase that was written in my previous comment and search in the titles.
Historically, monolithic mobile-first parts have been clocked up to 65W TDPs as desktop APUs later, but their primary focus is on performance/Watt because cooling and battery life are always more important than outright performance in a laptop part. That's why I'm agreeing with the rumour that these are 4x Zen5 and 8x Zen5c. Maybe I'm wrong, but at least you have my reasoning now.
Zen 4c is just a space-optimized Zen 4 core, rather than a clockspeed-optimized one. L3 is halved like the mobile Zen 4 parts.
- higher capacity means more hits in L2
- fewer misses to the much slower L3
Drawbacks compared to a private L2 are:- higher latency
- more wiring (probably a 4 port crossbar) requires more area
- lower bandwidth when more than one requester is active, i.e. when more than one core is accessing L2
Chips and Cheese did a deep dive on Gracemont in the 12900k. This was when it had 2 MB L2 per cluster. Let's compare to an AMD SOC that had 4 core clusters too. The latencies are:Let's look at bandwidth from the cache in a mulithreaded test.
Now this makes it clear why Intel chose a large, shared L2. Intel's L3 has poor bandwidth for a Gracemont cluster, but it doesn't matter because the L2 makes up for it.
As an aside, Gracemont has a large L1 I-cache which is something that the bigger cores should copy. This figure from Hirki et al's paper on Haswell's power consumption also shows the benefit of a larger L1.
It seems that a Gracemont cluster is more like a 4-thread core than 4 individual cores. I am sure that it technically isn't, but I get FX-8350 vibes...
Apple has enormous L1 caches and Power 6, the first 5 GHz CPU, had 64 KiB L1 caches. The Power 6, unlike Apple, didn't have the advantage of current processes, but it also had the advantage of a high power budget. The first Zen had a 64 KiB L1 I-cache as well.