Monday, February 19th 2024
AMD "Zen 5c" CCDs Made On More Advanced 3 nm Node Than "Zen 5"
AMD is reportedly building its upcoming "Zen 5" and "Zen 5c" CPU Core Dies (CCDs) on two different foundry nodes, a report by Chinese publication UDN, claims. The Zen 5 CCD powering the upcoming Ryzen "Granite Ridge" desktop processors, "Fire Range" mobile processors, and EPYC "Turin" server processors, will be reportedly built on the 4 nm EUV foundry node, a slightly more advanced node than the current 5 nm EUV the company is building "Zen 4" CCDs on. The "Zen 5c" CCD, or the chiplet with purely "Zen 5c" cores in a high density configuration; on the other hand, will be built on an even more advanced 3 nm EUV foundry node, the report says. Both CCDs will go into mass production in Q2-2024, with product launches expected across the second half of the year.
The "Zen 5c" chiplet has a mammoth 32 cores spread across two CCXs of 16 cores, each. Each CCX has 16 cores sharing a 32 MB L3 cache. It is to cram these 32 cores, each with 1 MB of L2 cache; and a total of 64 MB of L3 cache, that AMD could be turning to the 3 nm foundry node. Another reason could be voltages. If "Zen 4c" is anything to go by, the "Zen 5c" core is a highly compacted variant of "Zen 5," which operates at a lower voltage band than its larger sibling, without any change in IPC or instruction sets. The decision to go with 3 nm could be a move aimed at increasing clock speeds at those lower voltages, in a bid to generationally improve performance using clock speeds, besides IPC and core count. The EPYC processor with "Zen 5c" chiplets will feature no more than six such large CCDs, for a maximum core count of 192. The regular "Zen 5" CCD has just 8 cores in a single CCX, with 32 MB of L3 cache shared among the cores; and TSV provision for 3D Vertical Cache, to increase the L3 cache in special variants.
Sources:
UDN, Wccftech
The "Zen 5c" chiplet has a mammoth 32 cores spread across two CCXs of 16 cores, each. Each CCX has 16 cores sharing a 32 MB L3 cache. It is to cram these 32 cores, each with 1 MB of L2 cache; and a total of 64 MB of L3 cache, that AMD could be turning to the 3 nm foundry node. Another reason could be voltages. If "Zen 4c" is anything to go by, the "Zen 5c" core is a highly compacted variant of "Zen 5," which operates at a lower voltage band than its larger sibling, without any change in IPC or instruction sets. The decision to go with 3 nm could be a move aimed at increasing clock speeds at those lower voltages, in a bid to generationally improve performance using clock speeds, besides IPC and core count. The EPYC processor with "Zen 5c" chiplets will feature no more than six such large CCDs, for a maximum core count of 192. The regular "Zen 5" CCD has just 8 cores in a single CCX, with 32 MB of L3 cache shared among the cores; and TSV provision for 3D Vertical Cache, to increase the L3 cache in special variants.
78 Comments on AMD "Zen 5c" CCDs Made On More Advanced 3 nm Node Than "Zen 5"
They're space optimized like E cores. Extra fluff in the architecture is removed.
Would also make little sense to halve the cache on a core then put more on top, making heat transfer more difficult.
AMD: Here, get some identical cores with less cache and lower frequencies. Let's also use a more advance manufacturing node to get REAL Efficiency out of them.
In any case you come to my words by pointing at Skylake. It's exactly what I am saying. Cores with lower performance and newest features missing to make them smaller. AMD doesn't really need much smaller cores, because Zen P cores are already smaller than Intel's P cores and also it enjoys the advantage of node manufacturing.
Intel was always planning to keep that 8 P cores configuration for years and only increase the E cores number, because 8 P cores are more than enough today for about everything in consumer space.
My dude there's 12 pages of application testing done to get that average.
Training the OS? Unlike Zen with a software based driver scheduler for X3D that works most of the time, but is based on manual whitelists, likely for Zen C hybrid CPUs as well, Intel has a hardware based thread director.
You're talking about power consumption as if its relevant to your argument against E cores, when you say yourself AMD has a node advantage. 5nm TSMC is not comparable to 10nm Intel 7 superfin.
I guess we'll see when both Intel and AMD have their CPU "tiles" or "CCDs" next generation.
From what I understand there's major advancements made to tech with Arrow Lake, including RibbonFET gate all around transistors, foveros packaging and backside power delivery. Zen 6 is moving to comparable packaging tech which should fix the idle and low load efficiency issues with Zen 1-5.
www.phoronix.com/review/intel-14600k-14900k-linux/11
TPU forum though, so I'm using TPU testing, and synthetic server benchmarks isn't exactly "application" testing in the way people on this site understand it.
But yhea, AMD doesn't really have any reason to bring C-cores to the desktop unless Intel get a meaningful in MT.
appswhich isn't really that big of a number, although it's Linux so not exactly comparable even if you'd generally get better results for Intel (on Linux) as well.Read the actual TPU review, it has the AMD results too.
www.techpowerup.com/review/intel-core-i9-14900k/
It's not about feelings.
Thinking that every post is about feelings, only shows how YOU think and why YOU post, in this case. It's not about me. Don't project yourself on me. It doesn't work.They do. Marketing. They can't sell a 16 core CPU when Intel will be selling a "24 core" or a "32 core" CPU at the same price point, or even at a little higher price.
Marketing ≠ performance.
The testing doesn't lie.