Wednesday, February 21st 2024
Intel Xeon "Granite Rapids" Wafer Pictured—First Silicon Built on Intel 3
Feast your eyes on the first pictures of an Intel "Granite Rapids" Xeon processor wafer, courtesy of Andreas Schilling with HardwareLuxx.de. This is Intel's first commercial silicon built on the new Intel 3 foundry node, which is expected to be the company's final silicon fabrication node to implement FinFET technology; before the company switches to Nanosheets with the next-generation Intel 20A. Intel 3 offers transistor densities and performance competitive to TSMC N3 series, and Samsung 3GA series nodes.
The wafer contains square 30-core tiles, two of which make up a "Granite Rapids-XCC" processor, with CPU core counts going up to 56-core/112-threads (two cores left unused per tile for harvesting). Each of the 30 cores on the tile is a "Redwood Cove" P-core. In comparison, the current "Emerald Rapids" Xeon processor uses "Raptor Cove" cores, and is built on the Intel 7 foundry node. Intel is planning to overcome the CPU core-count deficit to AMD EPYC, including the upcoming EPYC "Turin" Zen 5 processors with their rumored 128-core/256-thread counts, by implementing several on-silicon fixed-function accelerators that speed up popular kinds of server workloads. The "Redwood Cove" core is expected to be Intel's first IA core to implement AVX10 and APX.
Source:
Andreas Schilling (Twitter)
The wafer contains square 30-core tiles, two of which make up a "Granite Rapids-XCC" processor, with CPU core counts going up to 56-core/112-threads (two cores left unused per tile for harvesting). Each of the 30 cores on the tile is a "Redwood Cove" P-core. In comparison, the current "Emerald Rapids" Xeon processor uses "Raptor Cove" cores, and is built on the Intel 7 foundry node. Intel is planning to overcome the CPU core-count deficit to AMD EPYC, including the upcoming EPYC "Turin" Zen 5 processors with their rumored 128-core/256-thread counts, by implementing several on-silicon fixed-function accelerators that speed up popular kinds of server workloads. The "Redwood Cove" core is expected to be Intel's first IA core to implement AVX10 and APX.
18 Comments on Intel Xeon "Granite Rapids" Wafer Pictured—First Silicon Built on Intel 3
They need 2 of those for top-end Xeon, right? I presume these are quite expensive wafers.
Even if all chips have 0 defects (impossible) you can make around 30-40 top-end CPUs from one wafer?
Compare density, frequency and power performance, not nm.
Our database has detailed info. Weighing transistors/die size is a simple way of figuring out density.
Don’t get me wrong, I love databases like the one at TPU but the website has to have the personnel to keep it accurate which is not an easy thing to do or have the money for a dedicated job position.
Edit: And your screen capture is for a specific CPU, not the highest density capabilities of a fab node. They are not always one in the same. Case in point, Zen 4 vs Zen 4c, same node but different densities.
Edit2: Also there are different versions of the same node. TPU still uses the old ‘plus’ sign moniker as in the upcoming hardware launches article and not the actual node names such as N4, N4P, N4X for the different TSMC 4 nm nodes for example. This info is also hard to come by and changes the density values. There is no such thing as ‘plus’ anymore.
This is not GraniteRapids!
The photos show EmeraldRapids with physically 33 RaptorCove cores.