Friday, September 27th 2024
AMD Ryzen 9 9950X3D and 9900X3D to Feature 3D V-cache on Both CCD Chiplets
Earlier this week, we got rumors that AMD is rushing in the Ryzen 7 9800X3D 8-core/16-thread "Zen 5" processor with 3D V-cache for a late-October debut. The 9800X3D succeeds the popular 7800X3D, and AMD probably hopes it will have a competitive gaming processor in time for Intel's Core Ultra 2-series "Arrow Lake-S" launch. In the previous article, it was reported that the higher core-count 9000X3D series processor models, the Ryzen 9 9950X3D and Ryzen 9 9900X3D, would arrive some time in Q1 2025, because it was reported that the chips have certain "new features" compared to their predecessors, the 7950X3D and 7900X3D. At the time, we even explored the possibility of AMD giving both 8-core CCDs on the processor 3D V-cache. Turns out, this is where things are headed.
A new report by Benchlife.info claims that the higher core-count 9950X3D and 9900X3D will implement 3D V-cache on both CCD chiplets, giving these processors an impressive 192 MB of L3 cache (96 MB per CCD), and 208 MB or 204 MB of "total cache" (L2+L3). The report also says that AMD is planning a Ryzen 5 9600X3D chip, its second attempt at taking on Intel's Core i5 lineup, following its very recent release of the Ryzen 5 7600X3D, which ended up 1-3% short of the Core i5-14600K in gaming workloads. There's no word on whether the 9600X3D will launch in October alongside the 9800X3D, or in Q1-2025 with the Ryzen 9 9000X3D series.
Documentation indicates that the max L3 cache is 96 MB, although the reference to SOC configuration leaves it unclear whether this is from 3DVCache, placed on top of the CCD, or otherwise.
The introduction of 3D V-cache on both CCDs of the 9950X3D and 9900X3D could be interesting, as both chiplets will be capable of gaming workloads at a uniform performance level. On the 7950X3D and 7900X3D, OS scheduler-level QoS logic ensure gaming workloads are scheduled to the CCD with the 3D V-cache, while multithreaded productivity workloads are allowed to spread across both CCDs.
Source:
Benchlife.info
A new report by Benchlife.info claims that the higher core-count 9950X3D and 9900X3D will implement 3D V-cache on both CCD chiplets, giving these processors an impressive 192 MB of L3 cache (96 MB per CCD), and 208 MB or 204 MB of "total cache" (L2+L3). The report also says that AMD is planning a Ryzen 5 9600X3D chip, its second attempt at taking on Intel's Core i5 lineup, following its very recent release of the Ryzen 5 7600X3D, which ended up 1-3% short of the Core i5-14600K in gaming workloads. There's no word on whether the 9600X3D will launch in October alongside the 9800X3D, or in Q1-2025 with the Ryzen 9 9000X3D series.
76 Comments on AMD Ryzen 9 9950X3D and 9900X3D to Feature 3D V-cache on Both CCD Chiplets
None of it does anything for cross-CCD scheduling problems - Ninja'd @RogueSix
So the question that reminds is clock speed affected or did they solve this problem also.
I'd still like both options available just becuase I want to see the actual difference not on games that do well on the current 7950X3D already but in games that don't behave without user intervention.
So I hope AMD releases both options with the single ccd option being slightly cheaper for academic reasons of course lol.
I don't know IF I will sell my 9950x
Let's wait for it on January 2025 :laugh:
If we are lucky, we could see them come to PC in 5 to 10 years.
Cloudflare switches to EPYC 9684X Genoa-X CPUs with 3D V-Cache — 145% faster than previous-gen Milan servers | Tom's Hardware (tomshardware.com)
That extra cache is basically useless for most of what I do, not worth the extra price and (likely) reduced clock speeds.The benefits are mostly for HPC and CFD workloads. And for those workloads, why would one even be using a Ryzen CPU? The dual-channel setup is already going to kill your performance anyway since those workloads are really memory bound.
For all others, it's actually a regression in performance due to the lower clocks. Here's the updated graph for Zen 4:
www.phoronix.com/review/amd-ryzen-7-7800x3d-linux/9
openbenchmarking.org/result/2304049-PTS-APRIL20258&sgm=1&hgv=Ryzen+7+7800X3D&sorI mean, that's mostly a Windows scheduler issue. Even Intel had to develop their own HW scheduler to work around that (which is pretty useless on Linux, as an example).Epyc X is not really used for games, and workloads that can be embarassingly parallel (like the ones Epyc X are used for) should not really do much cross-core communication at all to begin with.I don't think AMD would put so much effort in order to just work around Window's limitations. They haven't even updated Ryzen's desktop IO Die in a log time.
Maybe on Zen 6, as said before, but who knows.As I said above, it's mostly only for CFD and HPC stuff (apart from games). Most consumers will get no benefit from such extra cache.