Friday, December 27th 2024

NVIDIA GeForce RTX 5090 Features 16+6+7 Phase Power Delivery on 14-Layer PCB

Fresh details have surfaced about NVIDIA's upcoming flagship "Blackwell" graphics card, the GeForce RTX 5090, suggesting power delivery and board design changes compared to its predecessors. According to Benchlife, the new Blackwell-based GPU will feature a new 16+6+7 power stage design, departing from the RTX 4090's 20+3 phase configuration. The report confirms earlier speculation about the card's power requirements, indicating a TGP of 600 watts. This specification refers to the complete power allocation for the graphics subsystem, though the actual TDP of the GB202 chip might be lower. The RTX 5090 will ship with 32 GB of next-generation GDDR7 memory and utilize a 14-layer PCB, possibly due to the increased complexity of GDDR7 memory modules and power delivery. Usually, GPUs max out at 12 layers for high-end overclocking designs.

The upcoming GPU will fully embrace modern connectivity standards, featuring PCI Express 5.0 x16 interface compatibility and implementing a 12V-2×6 power connector design. We spotted an early PNY RTX 5090 model with 40 capacitors but an unclear power delivery setup. With additional power phases and more PCB layers, NVIDIA is pushing the power delivery and signal integrity boundaries for its next-generation flagship. While these specifications paint a picture of a powerful gaming and professional graphics solution, questions remain about the broader RTX 50 series lineup. The implementation of the 12V-2×6 connector across different models, particularly those below 200 W, remains unclear, so we have to wait for the CES-rumored launch.
Sources: Benchlife.info, via VideoCardz
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101 Comments on NVIDIA GeForce RTX 5090 Features 16+6+7 Phase Power Delivery on 14-Layer PCB

#101
TokyoQuaSaR
WirkoPCIe 5.0 makes things even more complicated. Given the memory chip layout, some lanes probably run under the memory chips and/or other lanes. This is quite unfavourable because these wires require a specific geometry (distance to ground, to other lanes etc).
Well there is a good amount of layers on the PCB for that but I agree PCI Gen5 doesn't make it easy. Basically 90% of the IOs have a very high bandwidth, which is actually not so frequent.
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