Tuesday, June 10th 2025
SK hynix Presents Future DRAM Technology Roadmap at IEEE VLSI 2025
SK hynix Inc. announced today that it presented a new DRAM technology roadmap for the next 30 years and the direction for a sustainable innovation at the IEEE VLSI symposium 2025 held in Kyoto, Japan. Cha Seon Yong, Chief Technology Officer (CTO) of SK hynix, delivered on June 10th a plenary session on "Driving Innovation in DRAM Technology: Towards a Sustainable Future".
In his speech, CTO Cha explained that it is increasingly difficult to improve performance and capacity with scaling through current technology platform. "In order to overcome such limitations, SK hynix will apply the 4F² VG (Vertical Gate) platform and 3D DRAM technology to technologies of 10-nanometer level or below with innovation in structure, material and components," he said. The 4F² VG platform is a next-generation memory technology that minimizes the cell area of DRAM and enables high-integration, high-speed and low-power through a vertical gate structure.
Currently, 6F2 cells are common, but by applying 4F2 cell and wafer bonding technology that puts the circuit part below the cell area, cell efficiency and electrical characteristics can be improved.
CTO Cha also introduced 3D DRAM as the main pillar for the future DRAM along with VG. CTO Cha said that although some in the industry warn of cost increase according to the number of layers stacked, it can be solved by constant technological innovation.
Along with structural breakthrough, the company will also strive to find a new growth engine by sophisticating technologies of critical materials and components of DRAM to lay foundation for the next 30 years.
"Until around 2010, DRAM technology was expected to face limitations at 20 nanometers, but with constant innovation, we have made it this far," said CTO Cha. "SK hynix will continue to guide the future of long-term technological innovation to be a milestone for young engineers in the field of DRAM and maintain cooperation within the industry to bring future of DRAM into reality."
On the last day of the event, Joodong Park, vice president who leads the Next Gen DRAM TF, will present his findings from a recent research on how VG and wafer bonding technology affect the electrical characteristics of DRAM.
In his speech, CTO Cha explained that it is increasingly difficult to improve performance and capacity with scaling through current technology platform. "In order to overcome such limitations, SK hynix will apply the 4F² VG (Vertical Gate) platform and 3D DRAM technology to technologies of 10-nanometer level or below with innovation in structure, material and components," he said. The 4F² VG platform is a next-generation memory technology that minimizes the cell area of DRAM and enables high-integration, high-speed and low-power through a vertical gate structure.
CTO Cha also introduced 3D DRAM as the main pillar for the future DRAM along with VG. CTO Cha said that although some in the industry warn of cost increase according to the number of layers stacked, it can be solved by constant technological innovation.
Along with structural breakthrough, the company will also strive to find a new growth engine by sophisticating technologies of critical materials and components of DRAM to lay foundation for the next 30 years.
"Until around 2010, DRAM technology was expected to face limitations at 20 nanometers, but with constant innovation, we have made it this far," said CTO Cha. "SK hynix will continue to guide the future of long-term technological innovation to be a milestone for young engineers in the field of DRAM and maintain cooperation within the industry to bring future of DRAM into reality."
On the last day of the event, Joodong Park, vice president who leads the Next Gen DRAM TF, will present his findings from a recent research on how VG and wafer bonding technology affect the electrical characteristics of DRAM.
6 Comments on SK hynix Presents Future DRAM Technology Roadmap at IEEE VLSI 2025
Think about this for a moment......that takes us out to 2055, at which point all computer components will likely be so small that they can be integrated onto a single, silicon-free "chip", will be totally wireless (including power), with autonomous updating and repairing, thereby doing away with what we now call a "PC/lappy/tablet/console ect"
what was Mr. Yong thinking when he made this plan ?????...
As a side note, this would be just 8 years before 1st contact... :D
Then someone mentally sane could explain
- Why SK Hynix is even proud about this lame announcement?????
Thanks.