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VIA Nano L2100

1
Cores
1
Threads
25 W
TDP
1800 MHz
Frequency
N/A
Boost
CNA
Codename
VIA nanoBGA2
Socket
Front
Front
Back
Back
VIA nanoBGA2
VIA nanoBGA2
The VIA Nano L2100 was a mobile processor with 1 core, launched in May 2008. It is part of the Nano L lineup, using the Isaiah (CNA) architecture with VIA nanoBGA2. Nano L2100 has 1 MB of L2 cache and operates at 1800 MHz. VIA is making the Nano L2100 on a 65 nm production node using 94 million transistors. The silicon die of the chip is not fabricated at VIA, but at the foundry of Fujitsu. The multiplier is locked on Nano L2100, which limits its overclocking potential.
With a TDP of 25 W, the Nano L2100 consumes only little energy. VIA's processor supports DDR2 and DDR3 memory with a single-channel interface. The highest officially supported memory speed is 1333 MT/s, but with overclocking (and the right memory modules) you can go even higher.
The SSE4 instruction set is not supported, which can cause problems with modern games, as they require that capability. Hardware virtualization is available on the Nano L2100, which greatly improves virtual machine performance.

Physical

Socket: VIA nanoBGA2
Foundry: Fujitsu
Process Size: 65 nm
Transistors: 94 million
Die Size: 63 mm²
Package: FC-BGA400

Processor

Market: Mobile
Production Status: End-of-life
Release Date: May 29th, 2008
Part#: unknown

Performance

Frequency: 1800 MHz
Turbo Clock: N/A
Base Clock: 200 MHz
Multiplier: 9.0x
Multiplier Unlocked: No
Voltage: 1.2 V
TDP: 25 W
Idle Power:0.5 W

Architecture

Codename: CNA
Generation: Nano L
(Isaiah (CNA))
Memory Support: DDR2, DDR3
Rated Speed: 1333 MT/s
Memory Bus: Single-channel
ECC Memory: No
Chipsets: VIA VX855, VIA VX900, VIA VN1000, VIA VX11

Core Config

# of Cores: 1
# of Threads: 1
SMP # CPUs: 1
Integrated Graphics: On certain motherboards (Chipset feature)

Cache

Cache L1: 128 KB
Cache L2: 1 MB

Features

  • MMX
  • SSE
  • SSE2
  • SSE3
  • SSSE3
  • AES
  • NX-bit
  • VT-x
  • SHA-1
  • SHA-256
  • x86-64
  • VIA Padlock
  • VIA Power Saver

Notes

VIA V4 Bus is a quad-pumped front side bus architecture, therefore Base Clock*4 gives the advertised FSB.

DRAM, Graphics, I/O, and Audio handled by the VIA MSP chipset used.
Jan 22nd, 2025 23:56 EST change timezone

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